mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
be1d5e0388
rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/grf_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0x20008000
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static struct rk3036_grf * const grf = (void *)GRF_BASE;
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#define DEBUG_UART_BASE 0x20068000
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extern void back_to_bootrom(void);
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void board_init_f(ulong dummy)
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{
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#ifdef EARLY_DEBUG
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/*
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* NOTE: sd card and debug uart use same iomux in rk3036,
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* so if you enable uart,
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* you can not boot from sdcard
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*/
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C3_MASK << GPIO1C3_SHIFT |
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GPIO1C2_MASK << GPIO1C2_SHIFT,
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GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
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GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
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rk_uart_init((void *)DEBUG_UART_BASE);
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#endif
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rockchip_timer_init();
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sdram_init();
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/* return to maskrom */
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back_to_bootrom();
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}
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/* Place Holders */
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void board_init_r(gd_t *id, ulong dest_addr)
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{
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/*
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* Function attribute is no-return
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* This Function never executes
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*/
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while (1)
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;
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}
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