huang lin be1d5e0388 rockchip: rk3036: Add core Soc start-up code ... rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288		2015-12-01 08:07:22 -07:00
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Kconfig	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
Makefile	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
reset_rk3036.c	rockchip: rk3036: Add Soc reset driver	2015-12-01 08:07:22 -07:00
save_boot_param.S	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
sdram_rk3036.c	rockchip: add rk3036 sdram driver	2015-12-01 08:07:22 -07:00
syscon_rk3036.c	rockchip: rk3036: Add a simple syscon driver	2015-12-01 08:07:22 -07:00