Marek Vasut 9a5a90ad9b ddr: altera: Add DDR2 support to Gen5 driver ... Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated by Quartus are named differently than the DDR3 ones, use anon unions to store them in the same structures, without growing their size. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>		2020-02-05 03:01:57 +01:00
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base_addr_a10.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
base_addr_ac5.h	arm: socfpga: fix SPL booting from fpga OnChip RAM	2018-11-29 12:45:15 +01:00
base_addr_s10.h	arm: socfpga: agilex: Add base address for Intel Agilex SoC	2020-01-07 14:38:33 +01:00
boot0.h	ARM: socfpga: Add boot trampoline for Arria10	2018-05-08 21:08:42 +02:00
clock_manager_agilex.h	arm: socfpga: agilex: Add clock wrapper functions	2020-01-07 14:38:33 +01:00
clock_manager_arria10.h	arm: socfpga: Convert clock manager from struct to defines	2020-01-07 14:38:33 +01:00
clock_manager_gen5.h	arm: socfpga: Convert clock manager from struct to defines	2020-01-07 14:38:33 +01:00
clock_manager_s10.h	arm: socfpga: Move Stratix10 and Agilex clock manager common code	2020-01-07 14:38:33 +01:00
clock_manager_soc64.h	arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz	2020-01-07 14:38:33 +01:00
clock_manager.h	arm: socfpga: agilex: Add clock wrapper functions	2020-01-07 14:38:33 +01:00
firewall.h	arm: socfpga: stratix10: Enable SMMU access	2020-01-07 14:38:34 +01:00
fpga_manager_arria10.h	spl: socfpga: Implement fpga bitstream loading with socfpga loadfs	2019-05-10 22:48:11 +02:00
fpga_manager_gen5.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
fpga_manager.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
freeze_controller.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
gpio.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
handoff_s10.h	arm: agilex: Add clock handoff offset for Agilex	2020-01-07 14:38:33 +01:00
mailbox_s10.h	arm: socfpga: stratix10: Add macros for mailbox's arguments	2018-12-20 17:12:25 +01:00
misc.h	arm: socfpga: Convert reset manager from struct to defines	2020-01-07 14:38:33 +01:00
nic301.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
pinmux.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
reset_manager_arria10.h	arm: socfpga: Convert reset manager from struct to defines	2020-01-07 14:38:33 +01:00
reset_manager_gen5.h	arm: socfpga: Convert reset manager from struct to defines	2020-01-07 14:38:33 +01:00
reset_manager_soc64.h	arm: socfpga: Move Stratix10 and Agilex reset manager common code	2020-01-07 14:38:33 +01:00
reset_manager.h	arm: socfpga: agilex: Add reset manager support	2020-01-07 14:38:33 +01:00
scan_manager.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
scu.h	ARM: socfpga: Fix Documentation errors in scu_registers	2018-05-18 10:30:47 +02:00
sdram_arria10.h	ARM: socfpga: Add DDR driver for Arria 10	2018-05-18 10:30:47 +02:00
sdram_gen5.h	ddr: altera: Add DDR2 support to Gen5 driver	2020-02-05 03:01:57 +01:00
sdram.h	ARM: socfpga: Add DDR driver for Arria 10	2018-05-18 10:30:47 +02:00
system_manager_arria10.h	arm: socfpga: Convert system manager from struct to defines	2020-01-07 14:38:33 +01:00
system_manager_gen5.h	arm: socfpga: Convert system manager from struct to defines	2020-01-07 14:38:33 +01:00
system_manager_soc64.h	arm: socfpga: Move Stratix10 and Agilex system manager common code	2020-01-07 14:38:33 +01:00
system_manager.h	arm: socfpga: agilex: Add system manager support	2020-01-07 14:38:33 +01:00
timer.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00