brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

spl: socfpga: Implement fpga bitstream loading with socfpga loadfs

Browse Source 
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Tien Fong Chee 2019-05-07 17:42:30 +08:00 committed by Marek Vasut
parent f61d529260
commit 1085bb3cba
3 changed files with 32 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
View File

@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
const char *get_fpga_filename(void);
int is_fpgamgr_early_user_mode(void);
int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
u32 offset);
void fpgamgr_program(const void *buf, size_t bsize, u32 offset);

31
arch/arm/mach-socfpga/spl_a10.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
* Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
*/
#include <common.h>
@ -23,6 +23,11 @@
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/fpga_manager.h>
#include <mmc.h>
#include <memalign.h>
#define FPGA_BUFSIZ 16 * 1024
DECLARE_GLOBAL_DATA_PTR;
@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
void spl_board_init(void)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
if (is_fpgamgr_user_mode()) {
int ret = config_pins(gd->fdt_blob, "shared");
if (ret)
return;
ret = config_pins(gd->fdt_blob, "fpga");
if (ret)
return;
} else if (!is_fpgamgr_early_user_mode()) {
/* Program IOSSM(early IO release) or full FPGA */
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
/* If the IOSSM/full FPGA is already loaded, start DDR */
if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
ddr_calibration_sequence();
if (!is_fpgamgr_user_mode())
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)

2
drivers/fpga/socfpga_arria10.c
View File

@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
static int is_fpgamgr_early_user_mode(void)
int is_fpgamgr_early_user_mode(void)
{
return (readl(&fpga_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;