Sean Anderson c33efafaf9 riscv: Rework riscv timer driver to only support S-mode ... The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>		2020-09-30 08:54:45 +08:00
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cache.c	riscv: fu540: Use correct API to get L2 cache controller base address	2020-08-25 09:33:16 +08:00
cpu.c	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
dram.c	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
Kconfig	riscv: Rework riscv timer driver to only support S-mode	2020-09-30 08:54:45 +08:00
Makefile	riscv: sifive: fu540: enable all cache ways from U-Boot proper	2020-07-03 15:09:06 +08:00
spl.c	riscv: sifive/fu540: spl: Rename soc_spl_init()	2020-08-14 14:38:53 +08:00