u-boot-brain/arch/riscv/cpu
Sean Anderson 768502e2a7 riscv: Clear pending IPIs on initialization
Even though we no longer call smp_function if an IPI was not sent by
U-Boot, we still need to clear any IPIs which were pending from the
execution environment. Otherwise, secondary harts will busy-wait in
secondary_hart_loop, instead of relaxing.

Along with the previous commit ("riscv: Use a valid bit to ignore
already-pending IPIs"), this fixes SMP booting on the Kendryte K210.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
..
ax25 riscv: Rework riscv timer driver to only support S-mode 2020-09-30 08:54:45 +08:00
fu540 riscv: Rework riscv timer driver to only support S-mode 2020-09-30 08:54:45 +08:00
generic riscv: Rework riscv timer driver to only support S-mode 2020-09-30 08:54:45 +08:00
cpu.c riscv: Clear pending IPIs on initialization 2020-09-30 08:54:52 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S Revert "riscv: Clear pending interrupts before enabling IPIs" 2020-09-30 08:54:52 +08:00
u-boot-spl.lds riscv: Add _image_binary_end for SPL 2020-06-04 09:44:08 +08:00
u-boot.lds riscv: Fix breakage caused by linker relaxation 2020-02-10 14:50:53 +08:00