mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
c33efafaf9
The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
51 lines
882 B
Plaintext
51 lines
882 B
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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config SIFIVE_FU540
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bool
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select ARCH_EARLY_INIT_R
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select SUPPORT_SPL
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select RAM
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select SPL_RAM if SPL
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply CMD_CPU
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imply SPL_CPU_SUPPORT
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply SMP
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imply CLK_SIFIVE
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imply CLK_SIFIVE_FU540_PRCI
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imply SIFIVE_SERIAL
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imply MACB
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imply MII
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imply SPI
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imply SPI_SIFIVE
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imply MMC
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imply MMC_SPI
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imply MMC_BROKEN_CD
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imply CMD_MMC
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imply DM_GPIO
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imply SIFIVE_GPIO
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imply CMD_GPIO
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imply MISC
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imply SIFIVE_OTP
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imply DM_PWM
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imply PWM_SIFIVE
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if ENV_IS_IN_SPI_FLASH
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config ENV_OFFSET
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default 0x505000
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config ENV_SIZE
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default 0x20000
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config ENV_SECT_SIZE
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default 0x10000
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endif # ENV_IS_IN_SPI_FLASH
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