Jagan Teki 6590bd8c47 clk: sunxi: Add Allwinner A10/A20 CLK driver ... Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>		2019-01-18 22:19:08 +05:30
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clk_a10.c	clk: sunxi: Add Allwinner A10/A20 CLK driver	2019-01-18 22:19:08 +05:30
clk_a64.c	reset: Add Allwinner RESET driver	2019-01-18 22:19:08 +05:30
clk_h3.c	clk: sunxi: Add Allwinner H3/H5 CLK driver	2019-01-18 22:19:08 +05:30
clk_sunxi.c	clk: Add Allwinner A64 CLK driver	2019-01-18 22:19:08 +05:30
Kconfig	clk: sunxi: Add Allwinner A10/A20 CLK driver	2019-01-18 22:19:08 +05:30
Makefile	clk: sunxi: Add Allwinner A10/A20 CLK driver	2019-01-18 22:19:08 +05:30