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6590bd8c47
Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
34 lines
790 B
Plaintext
34 lines
790 B
Plaintext
config CLK_SUNXI
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bool "Clock support for Allwinner SoCs"
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depends on CLK && ARCH_SUNXI
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select DM_RESET
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default y
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help
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This enables support for common clock driver API on Allwinner
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SoCs.
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if CLK_SUNXI
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config CLK_SUN4I_A10
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bool "Clock driver for Allwinner A10/A20"
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default MACH_SUN4I || MACH_SUN7I
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help
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This enables common clock driver support for platforms based
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on Allwinner A10/A20 SoC.
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config CLK_SUN8I_H3
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bool "Clock driver for Allwinner H3/H5"
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default MACH_SUNXI_H3_H5
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help
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This enables common clock driver support for platforms based
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on Allwinner H3/H5 SoC.
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config CLK_SUN50I_A64
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bool "Clock driver for Allwinner A64"
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default MACH_SUN50I
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help
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This enables common clock driver support for platforms based
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on Allwinner A64 SoC.
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endif # CLK_SUNXI
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