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https://github.com/brain-hackers/u-boot-brain
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6590bd8c47
Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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static struct ccu_clk_gate a10_gates[] = {
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[CLK_AHB_OTG] = GATE(0x060, BIT(0)),
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[CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
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[CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
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[CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
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[CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)),
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[CLK_USB_PHY] = GATE(0x0cc, BIT(8)),
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};
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static struct ccu_reset a10_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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};
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static const struct ccu_desc a10_ccu_desc = {
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.gates = a10_gates,
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.resets = a10_resets,
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};
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static int a10_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
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}
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static const struct udevice_id a10_ccu_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-ccu",
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.data = (ulong)&a10_ccu_desc },
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{ .compatible = "allwinner,sun7i-a20-ccu",
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.data = (ulong)&a10_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun4i_a10) = {
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.name = "sun4i_a10_ccu",
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.id = UCLASS_CLK,
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.of_match = a10_ccu_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a10_clk_bind,
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};
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