In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The SoCFPGA has reached a point where every single board code become
the same, since each and every single board is probed equally from OF.
Move the common board code into arch/arm/mach-socfpga/ .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Display altera sysid at startup, which was once removed during
the move.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Update the ZYBO device tree and enable config options that relate to the
added devices in the device tree.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init
is generated by the Vivado 2015.3 tools using the system configuration
provided by Digilent located on their website.
Update the kconfig so that the defconfig is not overrided to use the
custom init ps7_init_gpl target by default.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo.
And create aliases for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional. For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC). A further rework and consolidation of the
functions should be done at a later date.
Tested on Beaglebone Black (SD and eMMC boot).
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
kylin board use rk3036 SOC, 512M sdram, 8G emmc.
This add some basic files required to allow the board
to output serial message and can run command(mmc info etc).
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
only rank large than 1, we will use cs1_row, so check rank, when
rank larger than 1, we set the cs1_row.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
GCC 5.x does not like sizeof(array_variable) and errors out. Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun <yorksun@freescale.com>
This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.
Changes:
1) Add a 1 ms wait for L3 timeout error trigger
2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add some spaces around operators.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to extend the range check in clock_twi_onoff, resulting in
the clock not getting enabled.
The range-check is not needed at all, since clock_twi_onoff only gets
called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE
is set and Kconfig already only allows these on sun6i / sun7i.
This commit removes the range-check all together fixing i2c bus 4 and 5
not working on sun7i.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
[hdegoede@redhat.com] Remove range check instead of extending it
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add dts and defconfig for h8homletv2 board.
H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.
A83T patches are tested on this board.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.
This is not yet included in kernel.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.
SMP is not yet supported.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds support of USB 2.0 storage media on AXS10x boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:
"
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
}
"
Without this patch, we will always encounter "Wrong LCD interface".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
based on DM requirement
- Do not enable EMIO DT support by default
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function triggers the registration of the dwmmc driver on SoCFPGA,
but this is not needed in case the driver is correctly probed from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:
- SPI NOR
- eMMC
- Ethernet
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
We now want to make sure that we have the platform data for NS16550 when
we do not have OF_CONTROL set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present an incorrect #if term is preventing this data from being compiled
in. All tegra boards use driver model for serial, so we can just drop this.
Fixes: fde7e18938 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
There are two numbering schemes for the RPi revision values; old and new
scheme. The values within each scheme overlap. Hence, it doesn't make
sense to have absolute/global names for the revision IDs. Get rid of the
names and just use the raw revision/type values to set up the array of
per-revision data.
This change makes most sense when coupled with the next change. However,
it's split out so that the mechanical cut/paste is separate from the
logic changes for easier review and problem bisection.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
With gcc-5.x we get warning about inline non-static functions referring to
static elements.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Introduce chosen node and specify uart0 to be used as serial console.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the commit 'c7b9686d5d48 ("ns16550: unify serial_omap")' all
TI platforms are broken with DM/DT boot as ns16550 driver expects
reg-shift from DT which is not populated for TI platforms.
Earlier it worked as it was hard coded to 2 in serial-omap
driver. So adding the reg-shift to serial nodes for dra7, am4372
and am33xx dtsi files. Tested this patch on am437x-sk-evm,
am437x-gp-evm, am335x-boneblack, dra74x-evm and dra72x-evm.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Before continue, check return value of strict_strtoul.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed the prom_relocate() function in start.S file by reserving memory in
the board_init_f sequence and saving the offset to the __prom_start_reloc
variable. This value is used as the destination when relocating the PROM.
Add the prom_init() function to the end of the board_init_r sequence.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Introduce the CONFIG_SYS_TIMER_* macros in include/asm/config.h to make use
of the generic timer infrastructure in lib/time.c.
Created a timer_init() function to initialize the timer hardware and update
the #ifdef in board_init_f to allow this function to be called during the
start-up sequence.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Reworked the LEON2 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON2 boards.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Reworked the LEON3 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON3 boards.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Initial ground work in preperation for generic board initialization
code for the SPARC architecture.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX
option to select which serial port the console will use.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the
panic function can use DEBUG_UART driver. drivers/serial/serial.c set this
flag before calling this function, preventing DEBUG_UART code from running.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Remove the version_string variable from start.S file. A weak variable
is also set in the cmd_version.c file. No need for architecture override.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
