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sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs

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According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.

Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Hans de Goede 2015-11-20 19:29:49 +01:00
parent 789fa275b3
commit cbc1a91afb
1 changed files with 0 additions and 4 deletions
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4
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
#if defined CONFIG_MACH_SUN8I_H3
#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
#else
#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
#endif
#define AXI_GATE_OFFSET_DRAM 0