Commit Graph

18604 Commits

Author SHA1 Message Date
Weijie Gao
e58e68d93e mmc: mtk-sd: assign plat->cfg.f_max with a correct value
Currently this driver does not set the value of plat->cfg.f_max, which
results in that MMC framework will always run at the lowest frequency.

This patch sets plat->cfg.f_max to the maximum allowed frequency, which
equals to the source clock frequency.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:27 +01:00
Weijie Gao
2a505cd1c7 mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCs
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.

This patch adds default pad control settings for mt7620_compat.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:27 +01:00
Weijie Gao
f875a12578 mmc: mtk-sd: fix sclk cycles shift value
It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.

This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:27 +01:00
Weijie Gao
17ade70b6a net: add ethernet driver for MediaTek MT7620 SoC
This patch adds  ethernet driver for MediaTek MT7620 SoC.

The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in
7-port switch and two xMII interfaces (can be MII/RMII/RGMII).

The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be
configured to connect to either the intergrited FE PHY, or the xMII.
Port 5 always connects to the xMII. Port 6 is the CPU port.

This driver supports MT7530 giga switch connects to port 5.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:27 +01:00
Weijie Gao
b4f214f044 phy: add USB PHY driver for MediaTek MT7620 SoC
This patch adds USB PHY driver for MediaTek MT7620 SoC

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
2db6fba051 spi: add spi controller support for MediaTek MT7620 SoC
This patch adds spi controller support for MediaTek MT7620 SoC.

The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
ca610ddf97 gpio: add GPIO controller driver for MediaTek MT7620 SoC
This patch adds GPIO controller driver for MediaTek MT7620 SoC

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
bba4ec81fd watchdog: add watchdog driver for MediaTek MT7620 SoC
This patch adds watchdog support for the Mediatek MT7620 SoC

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
a9a3a3aafc pinctrl: mtmips: add support for MediaTek MT7620 SoC
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
d9a5da72d7 clk: add clock driver for MediaTek MT7620 SoC
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Weijie Gao
2161f1fcb3 serial: add uart driver for MediaTek MT7620 SoC
This patch adds uart support for MediaTek MT7620 and earlier SoCs.

The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate instead of the
original two 8-bit registers (DLL and DLM).

The driver supports of-platdata which is useful for tiny SPL.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Tom Rini
abd95385e7 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.git 2021-01-22 16:01:27 -05:00
Shawn Lin
9ddc0787bd pci: Add Rockchip dwc based PCIe controller driver
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Shawn Lin
6ec62b6ca6 phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Michal Simek
b2e35a6f12 mmc: xenon_sdhci: Remove duplicated macros
There is no need to define the same macros in drivers.
All macros have been added by commit 17a42abb40 ("mmc: Define timing
macro's").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-20 08:34:53 +01:00
Marek Vasut
6f1e668d96 net: dwc_eth_qos: Pad descriptors to cacheline size
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-01-19 09:15:02 -05:00
Marek Vasut
dd70ff4815 net: ks8851: Reset internal RXFC count on bad packet
A sporadic condition occurs when the "bad packet" error is triggered
repeatedly, which results in "bad packet" messages scrolling on the
console during transfer. To avoid triggering this, reset the internal
RXFC count on the first occurance of the "bad packet", which forces
the code to re-read the RX packet count from the MAC, and prevents
any additional "bad packet" messages if there are no more packets in
the MAC. Also print better debug information if this condition occurs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>
2021-01-19 09:15:02 -05:00
Hongwei Zhang
0be3d1fafb net: ftgmac100: Read and retain MAC address
Read and retain MAC address across flash and QEMU support.

Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
2021-01-19 09:15:02 -05:00
Ian Ray
3f8905ade2 net: e1000: implement eth_write_hwaddr for DM_ETH
Implement programming MAC address to the hardware also for device model
configuration.

Fixes: b565b18a29 ("board: ge: bx50v3: Enable DM for PCI and ethernet")
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2021-01-19 09:15:01 -05:00
Weijie Gao
63779b2407 timer: mtk_timer: initialize the timer before use
The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.

This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.

This patch adds the initialization code to avoid them.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18 15:23:06 -05:00
Heinrich Schuchardt
97bf73762f pinctrl: mediatek: correct error handling
If no GPIO controller is found, the return value should not depend on a
random value on the stack. Initialize variable ret.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-01-18 15:23:06 -05:00
Heinrich Schuchardt
c65b7d1acf mtd: remove drivers/mtd/mw_eeprom.c
drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write()
and mw_eeprom_read() have incorrect loop conditions:

	while (len <= 2) {

CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18 15:23:06 -05:00
Heinrich Schuchardt
80b1ef942d drivers: qe: avoid double free()
Avoid calling free(addr) twice if the device for ucode is not found.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18 15:23:06 -05:00
Heinrich Schuchardt
f11b38e3ae mmc: fsl_esdhc_spl: remove superfluous free()
Freeing a buffer before calling hang() is superfluous. Removing the call
reduces the SPL size.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-18 15:23:06 -05:00
Heinrich Schuchardt
4908067b8f dma: bcm6348: incorrect buffer allocation
Calling calloc() for 0 members does not make any sense.
Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally
unreasonable.

The current code will lead to a NULL dereference in bcm6348_iudma_enable().

The assignments for ch_priv->busy_desc are obviously swapped.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18 15:23:06 -05:00
Tim Harvey
2767d881f0 power: pmic: add driver for Monolithic Power mp5416
This adds basic register access and child regulator binding
for the Monolithic MP5416 Power Management IC which integrates
four DC/DC switching converters and five LDO regulators.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-01-18 15:23:06 -05:00
Chia-Wei, Wang
4a84cf06aa aspeed: Add AST2600 platform support
Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.

However, currently the patch supports only the booting from
memory-mapped SPI flash.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:23:06 -05:00
Chia-Wei, Wang
9fc21086b7 reset: aspeed: Add AST2600 reset support
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:23:06 -05:00
Chia-Wei, Wang
337d95c4aa wdt: aspeed: Add AST2600 watchdog support
AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.

A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:23:05 -05:00
Dylan Hung
fde9314346 ram: aspeed: Add AST2600 DRAM control support
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:19:15 -05:00
Ryan Chen
a3c85990c3 clk: aspeed: Add AST2600 clock support
This patch adds the clock control driver
for the AST2600 SoC.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18 15:14:56 -05:00
Kate Liu
161df94b3c mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support
Add Cortina Access parallel Nand support for CAxxxx SOCs

Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18 15:14:34 -05:00
Harm Berntsen
7b4fe6dac1 mmc: Only retrieve cd pin when GPIO is enabled
The driver only needs to retrieve the pin for the ACPI info. The driver
itself works without depending on GPIO.

Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18 15:14:15 -05:00
Fabien Parent
c9d7e79f02 clk: mediatek: Add MT8183 clock driver
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183
SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18 15:14:13 -05:00
Tom Rini
ae3d8b6c40 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- R-Car pinctrl updates
2021-01-18 12:38:22 -05:00
Tom Rini
59e4e391df Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
  - Select TIMER_EARLY to avoid infinite recursion for Trace.
2021-01-18 08:04:28 -05:00
Lad Prabhakar
8096e2426d pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Lad Prabhakar
cc6aa80dd1 pinctrl: renesas: Make sure the pin type is updated after setting the MUX
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).

So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.

This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.

This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Padmarao Begari
2f27c9219e clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
1b4593826c net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
6f0b237372 net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.

The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Pragnesh Patel
bc8d12bfd8 riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:32 +08:00
Heinrich Schuchardt
f5abd8a616 ram: k3-j721e: rename BIT_MASK()
The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid
name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h
to LPDDR4_BIT_MASK().

Remove superfluous parantheses.
Remove superfluous comparison to 0.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
bcb0203c61 mtd: misplaced log.h and dm/devres.h
log.h and dm/devres.h are U-Boot includes. So placing them
behind #ifndef __UBOOT__ does not make any sense.

Fixes: f7ae49fc4f ("common: Drop log.h from common header")
Fixes: 61b29b8268 ("dm: core: Require users of devres to include the header")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Vabhav Sharma
67b2ed0243 drivers: serial: probe all uart devices
U-Boot DM model probe only single device at a time
which is enabled and configured using device tree
or platform data method.

PL011 UART IP is SBSA compliant and firmware does the
serial port set-up, initialization and let the kernel use
UART port for sending and receiving characters.

Normally software talk to one serial port time but some
LayerScape platform require all the UART devices enabled
in Linux for various use case.

Adding support to probe all enabled serial devices like SBSA
compliant PL011 UART ports probe and initialization by firmware.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-01-16 14:49:09 -05:00
Vabhav Sharma
a59153dfeb dm: core: add function uclass_probe_all() to probe all devices
Support a common method to probe all devices associated with uclass.

This includes data structures and code for finding the first device and
looping for remaining devices associated with uclasses (groups of devices
with the same purpose, e.g. all SERIAL ports will be in the same uclass).

An example is SBSA compliant PL011 UART IP, where firmware does the serial
port initialization and prepare uart device to let the kernel use it for
sending and reveiving the characters.SERIAL uclass will use this function
to initialize PL011 UART ports.

The feature is enabled with CONFIG_DM.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-01-16 14:49:09 -05:00
Nishanth Menon
2d572ede11 power: regulator: Kconfig: add a dependency for POWER_SUPPORT for SPL
power/regulator will not be built if just CONFIG_SPL_DM_REGULATOR is
enabled. It needs CONFIG_SPL_POWER_SUPPORT to be enabled as well.

For example, if we just need a GPIO regulator in SPL:
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y

Will not suffice, since the entire regulator build for SPL depends on
CONFIG_SPL_POWER_SUPPORT. Elaborate that information in the Kconfig
dependency.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-16 14:49:09 -05:00
Marcin Juszkiewicz
9a3122f769 Kconfig: simple panel requires backlight
During build of simple panel driver backlight is needed so let's enable
it:

aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_set_backlight':
u-boot/drivers/video/simple_panel.c:43: undefined reference to `backlight_set_brightness'
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_enable_backlight':
u-boot/drivers/video/simple_panel.c:28: undefined reference to `backlight_enable'

Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2021-01-16 11:58:49 -05:00
Marek Szyprowski
92f1c89d0a disk: dos: rename write_mbr_partition to write_mbr_sector
write_mbr_partition() function name is a bit misleading, so rename it to
write_mbr_sector(). This is a preparation for adding code for writing a
complete MBR partition layout.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2021-01-15 14:38:00 -05:00
Ovidiu Panait
c65abc70fb common: board_r: Drop initr_bbmii wrapper
Add a return value to bb_miiphy_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00