reset: aspeed: Add AST2600 reset support

Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
This commit is contained in:
Chia-Wei, Wang 2020-12-14 13:54:26 +08:00 committed by Tom Rini
parent 337d95c4aa
commit 9fc21086b7
4 changed files with 188 additions and 0 deletions

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@ -81,6 +81,15 @@ config RESET_AST2500
Say Y if you want to control reset signals of different peripherals
through System Control Unit (SCU).
config RESET_AST2600
bool "Reset controller driver for AST2600 SoCs"
depends on DM_RESET
default y if ASPEED_AST2600
help
Support for reset controller on AST2600 SoC.
Say Y if you want to control reset signals of different peripherals
through System Control Unit (SCU).
config RESET_ROCKCHIP
bool "Reset controller driver for Rockchip SoCs"
depends on DM_RESET && ARCH_ROCKCHIP && CLK

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@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

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@ -0,0 +1,108 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020 ASPEED Technology Inc.
*/
#include <common.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
#include <reset.h>
#include <reset-uclass.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2600.h>
struct ast2600_reset_priv {
struct ast2600_scu *scu;
};
static int ast2600_reset_request(struct reset_ctl *reset_ctl)
{
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
reset_ctl->dev, reset_ctl->id);
return 0;
}
static int ast2600_reset_free(struct reset_ctl *reset_ctl)
{
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
reset_ctl->dev, reset_ctl->id);
return 0;
}
static int ast2600_reset_assert(struct reset_ctl *reset_ctl)
{
struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
struct ast2600_scu *scu = priv->scu;
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
if (reset_ctl->id < 32)
writel(BIT(reset_ctl->id), scu->modrst_ctrl1);
else
writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2);
return 0;
}
static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
{
struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
struct ast2600_scu *scu = priv->scu;
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
if (reset_ctl->id < 32)
writel(BIT(reset_ctl->id), scu->modrst_clr1);
else
writel(BIT(reset_ctl->id - 32), scu->modrst_clr2);
return 0;
}
static int ast2600_reset_probe(struct udevice *dev)
{
int rc;
struct ast2600_reset_priv *priv = dev_get_priv(dev);
struct udevice *scu_dev;
/* get SCU base from clock device */
rc = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
if (rc) {
debug("%s: clock device not found, rc=%d\n", __func__, rc);
return rc;
}
priv->scu = devfdt_get_addr_ptr(scu_dev);
if (IS_ERR_OR_NULL(priv->scu)) {
debug("%s: invalid SCU base pointer\n", __func__);
return PTR_ERR(priv->scu);
}
return 0;
}
static const struct udevice_id ast2600_reset_ids[] = {
{ .compatible = "aspeed,ast2600-reset" },
{ }
};
struct reset_ops ast2600_reset_ops = {
.request = ast2600_reset_request,
.rfree = ast2600_reset_free,
.rst_assert = ast2600_reset_assert,
.rst_deassert = ast2600_reset_deassert,
};
U_BOOT_DRIVER(ast2600_reset) = {
.name = "ast2600_reset",
.id = UCLASS_RESET,
.of_match = ast2600_reset_ids,
.probe = ast2600_reset_probe,
.ops = &ast2600_reset_ops,
.priv_auto = sizeof(struct ast2600_reset_priv),
};

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@ -0,0 +1,70 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) ASPEED Technology Inc.
*/
#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_
#define _ABI_MACH_ASPEED_AST2600_RESET_H_
#define ASPEED_RESET_FSI (59)
#define ASPEED_RESET_RESERVED58 (58)
#define ASPEED_RESET_RESERVED57 (57)
#define ASPEED_RESET_SD (56)
#define ASPEED_RESET_ADC (55)
#define ASPEED_RESET_JTAG_MASTER2 (54)
#define ASPEED_RESET_MAC4 (53)
#define ASPEED_RESET_MAC3 (52)
#define ASPEED_RESET_RESERVE51 (51)
#define ASPEED_RESET_RESERVE50 (50)
#define ASPEED_RESET_RESERVE49 (49)
#define ASPEED_RESET_RESERVE48 (48)
#define ASPEED_RESET_RESERVE47 (47)
#define ASPEED_RESET_RESERVE46 (46)
#define ASPEED_RESET_I3C5 (45)
#define ASPEED_RESET_I3C4 (44)
#define ASPEED_RESET_I3C3 (43)
#define ASPEED_RESET_I3C2 (42)
#define ASPEED_RESET_I3C1 (41)
#define ASPEED_RESET_I3C0 (40)
#define ASPEED_RESET_I3C_DMA (39)
#define ASPEED_RESET_RESERVED38 (38)
#define ASPEED_RESET_PWM (37)
#define ASPEED_RESET_PECI (36)
#define ASPEED_RESET_MII (35)
#define ASPEED_RESET_I2C (34)
#define ASPEED_RESET_RESERVED33 (33)
#define ASPEED_RESET_LPC_ESPI (32)
#define ASPEED_RESET_H2X (31)
#define ASPEED_RESET_GP_MCU (30)
#define ASPEED_RESET_DP_MCU (29)
#define ASPEED_RESET_DP (28)
#define ASPEED_RESET_RC_XDMA (27)
#define ASPEED_RESET_GRAPHICS (26)
#define ASPEED_RESET_DEV_XDMA (25)
#define ASPEED_RESET_DEV_MCTP (24)
#define ASPEED_RESET_RC_MCTP (23)
#define ASPEED_RESET_JTAG_MASTER (22)
#define ASPEED_RESET_PCIE_DEV_OE (21)
#define ASPEED_RESET_PCIE_DEV_O (20)
#define ASPEED_RESET_PCIE_RC_OE (19)
#define ASPEED_RESET_PCIE_RC_O (18)
#define ASPEED_RESET_RESERVED17 (17)
#define ASPEED_RESET_EMMC (16)
#define ASPEED_RESET_UHCI (15)
#define ASPEED_RESET_EHCI_P1 (14)
#define ASPEED_RESET_CRT (13)
#define ASPEED_RESET_MAC2 (12)
#define ASPEED_RESET_MAC1 (11)
#define ASPEED_RESET_RESERVED10 (10)
#define ASPEED_RESET_RVAS (9)
#define ASPEED_RESET_PCI_VGA (8)
#define ASPEED_RESET_2D (7)
#define ASPEED_RESET_VIDEO (6)
#define ASPEED_RESET_PCI_DP (5)
#define ASPEED_RESET_HACE (4)
#define ASPEED_RESET_EHCI_P2 (3)
#define ASPEED_RESET_RESERVED2 (2)
#define ASPEED_RESET_AHB (1)
#define ASPEED_RESET_SDRAM (0)
#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */