Currently the AHB1 clock speed is configured as 200MHz by
the SPL, but this causes a subtle and hard to reproduce data
corruption in SRAM C (for example, this can't be easily
detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1
as 200MHz, as can be verified by running the devmem2 tool
in the system running the Allwinner's kernel 3.10.x:
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
0x1C20054: AHB1_APB1_CFG_REG = 0x3180
0x1C20058: APB2_CFG_REG = 0x1000000
0x1C2005C: AHB2_CFG_REG = 0x1
However the FEL mode uses more conservative settings (100MHz
for AHB1):
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
0x1C20054: AHB1_APB1_CFG_REG = 0x3190
0x1C20058: APB2_CFG_REG = 0x1000000
0x1C2005C: AHB2_CFG_REG = 0x0
It is yet to be confirmed whether faster AHB1/AHB2 clock settings
can be used safely if we initialize the AXP803 PMIC instead of
using reset defaults. But in order to resolve the data corruption
problem right now, it's best to downclock AHB1 to a safe level.
Note that this issue only affects the SPL, which is not fully
supported on Allwinner A64 yet and it should not affect the boot0
usage (unless somebody can confirm SRAM C corruption with the
boot0 too).
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 372286217f ("MIPS: Split I & D cache line size config")
Commit fb64cda579 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda579 ("MIPS: Abstract cache op loops with a macro")
In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now]
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable Spread Spectrum for the MPU by calculating the required
values and setting the registers accordingly.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
add missing CM_CLKMODE_DPLL_SSC_ACK_MASK,
CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and
CM_CLKMODE_DPLL_SSC_TYPE_MASK
defines. Used for enabling spread spectrum.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.
The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This code auto-detects the best-match FDT file name, but it should
respect the user's choice if "fdt_file" environment is found in a
saved set of environments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This function is shared between PH1-LD11 and PH1-LD20. The difference
is the boot-mode latch for the USB boot mode.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device. They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Just sort the board entries, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.
Signed-off-by: Pavel Machek <pavel@denx.de>
Both comments look like being copy & paste errors.
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.
Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
.space 1000
.word 0x12345678
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
start.S (arm64) and
vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).
For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.
[1] https://github.com/apritzel/pine64/tree/master/tools
END
Reviewed-by: Tom Rini <trini@konsulko.com>
To quit an EFI application we will need logic to jump to the caller
of a function without returning from the function we called into,
so we need setjmp/longjmp functionality.
This patch introduces a trivial implementation of these that I
verified works on armv7, thumb2 and aarch64.
Signed-off-by: Alexander Graf <agraf@suse.de>
Add some tests for the new open drain setting feature of the GPIO
uclass, and extend the capabilities of the sandbox GPIO driver
accordingly.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).
Each GPIO bank is identified by its own entry in the device tree, i.e.
gpio-controller@fc00 {
#gpio-cells = <2>;
compatible = "fsl,pq3-gpio";
reg = <0xfc00 0x100>
}
By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).
The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.
The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Replace a number of array length calculations with the ARRAY_SIZE()
macro, for clarity.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
u32 rcw_tmp;
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
With the existing code, function symbols are defined in .text, and the
body is defined in .text.xxx. This causes (at least some version of) the
linker not to emit the function body into the final binary, since it's
part of a different section to the symbols being referenced. This of
course causes a wide variety of failures.
This change moves the push/pop-section directives before the function
symbols, and after any relate ENDPROC macro invocations, so that symbols
and bodies are all in the "pushed" sections, and thus the function bodies
are emitted into the binary.
This solves (at least) the boot problems currently seen on Tegra systems
that use SPL (i.e. all ARMv7 Tegras).
Fixes: 13b0a91a6d ("arm: lib: Split asm symbols into different .text subsections")
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.
Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.
Right now to give a default watchdog behaviour "Device reset" is
being selected.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.
The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.
The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.
Fixes: 09cc14f4bc ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>
Split each symbol in lib1funcs into different .text.foo section instead
of placing all of them into plain .text . This allows the linker to collect
and discard unused assembler symbols.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import functions into lib1funcs.S which are required for Thumb1
build. These functions come from gcc 5.3.1 release.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which
is needed when doing Thumb1 builds.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fix the following warning when building for thumb2 target by tweaking the
instruction syntax:
Warning: conditional infixes are deprecated in unified syntax
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This function is for some toolchains, which generate _udivmoddi4()
for 64 bit division.
Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This assembler source won't build in Thumb2 mode, so fix it adding
the necessary Thumb2 conditional macros from unified.h .
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.
Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the libgcc shift operations with Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import unified.h from Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.
Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines the
CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all
of the assembler files. This is mandatory.
Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and
only if Thumb2 build is enabled. This macro is checked by unified.h
and toggles between ARM and Thumb2 variant of the instructions in the
assembler source files.
Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the
new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between
more optimal and more dense codepaths which work on armv5 and newer
and less optimal codepaths which work on armv4 and possible armv3m.
Tegra2 needs the same special handling as it does in arch/arm/Makefile
to cater for the arm720t boot core.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce new helper Kconfig option, which is automatically set to
the version of ARM architecture for which the U-Boot is built. This
is useful when selecting tuning options in the libgcc imported from
Linux kernel.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Select the config option, since this board is ARM64.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
The arm946es is armv5te , so use -march=armv5te instead of armv4t.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.
Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.
U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds the bare minimum code to support Tegra186, with UART and eMMC
working.
The empty gpio.h is required because <asm/gpio.h> includes it. A future
cleanup round may be able to solve this for all Tegra generations at once.
mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but
instead to defer everything to mach-tegra/tegra186/Makefile. This allows
the SoC code to pick-and-choose which of the C files in the "common"
mach-tegra/ directory to compile in based on the SoC's needs. Most of the
code is not valid for Tegra186, and this approach removes the need for
mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach
may be applied to all other Tegra SoCs in a future cleanup round.
board186.c is introduced to replace board.c and board2.c. These files
currently contain a slew of SoC- and board-specific code that is not
valid for Tegra186. This approach avoids adding yet more ifdefs to those
files. A future cleanup round may refactor most of board*.c into board-/
SoC-specific functions files thus allowing the top-level functions like
board_init_early_f to be shared again.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra186's MMC controller needs to be explicitly identified. Add another
compatible value for it.
Tegra186 will use an entirely different clock/reset control mechanism to
existing chips, and will use standard clock/reset APIs rather than the
existing Tegra-specific custom APIs. The driver support for that isn't
ready yet, so simply disable all clock/reset usage if compiling for
Tegra186. This must happen at compile time rather than run-time since the
custom APIs won't even be compiled in on Tegra186. In the long term, the
plan would be to convert the existing custom APIs to standard APIs and get
rid of the ifdefs completely.
The system's main eMMC will work without any clock/reset support, since
the firmware will have already initialized the controller in order to
load U-Boot. Hence the driver is useful even in this apparently crippled
state.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.
TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h
Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.
This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:
https://patchwork.linux-mips.org/patch/12564/
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For odroid-c2 (arch-meson) for now disable designware eth as meson
now needs to do some harder GPIO work.
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
lib/efi_loader/efi_disk.c
Modified:
configs/odroid-c2_defconfig
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since 1e6ad55c05 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add minimal dts support for AM335x-ICEv2 board
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>