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ARM: OMAP4+: Fix DPLL programming sequence

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All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Lokesh Vutla 2016-05-23 13:31:19 +05:30 committed by Tom Rini
parent 87c2f76f3f
commit 9b77b19178
1 changed files with 5 additions and 3 deletions
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8
arch/arm/cpu/armv7/omap-common/clocks-common.c
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@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
bypass_dpll(base);
goto setup_post_dividers;
}
}
@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
writel(temp, &dpll_regs->cm_clksel_dpll);
setup_post_dividers:
setup_post_dividers(base, params);
/* Lock */
if (lock)
do_lock_dpll(base);
setup_post_dividers:
setup_post_dividers(base, params);
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);