This is an init function so move it out of the common header. Avoid using
the typedef so that we don't have to include the global_data header file.
Also tidy up the function style in comments while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
The QorIQ eSDHC controller supports two reference clocks. They are
platform clock and periperhal clock. The global variable sdhc_clk
has already been used for platform clock.
This patch is to add another global variable sdhc_per_clk for
periperhal clock, which provides higher frequency and is required
to be used for SD UHS and eMMC HS200/HS400 speed modes.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The below patch added eSDHC periperhal clock code initially.
2d9ca2c mmc: fsl_esdhc: Add peripheral clock support
The purpose was to fix up device tree properties "peripheral-frequency"
so that linux could get the periperhal clock by it.
However the implementation on both u-boot and linux was only
for a Freescale SDK release. The linux part implementation had never
been upstreamed. These code should not have been exist on u-boot
mainline.
Let's remove the powerpc part changes but keep the changes in
fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized
to support SD UHS and eMMC HS200/HS400 speed modes for current
Layerscape ARM platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The MPC8309 has two gpio controllers (which is already correctly
reflected in its struct immap definition).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Allow drivers/spi/mpc8xxx_spi.c to be built for an mpc8309 target.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
This complements commit 068789773d which did the conversion for
mpc85xx.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
The mpc8309 is also affected by the "Manual Asynchronous CMD12 abort
operation causes protocol violations" erratum, though it is enumerated
as eSDHC16 in the errata sheet for mpc8309.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.
Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
These are used by only one arch and only within a single file. Drop the
declarations from the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in time.h so move them over and add comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.
Use the vsprintf.h include file explicitly where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are a few whitespace problems with this code. Tidy them up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The clock.h was to define mxc_get_clock() providing clock value
to fsl_esdhc driver. Since fsl_esdhc driver is using global data
gd->arch.sdhc_clk directly now, we can remove this file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add DM support for Freescale PowerPC sata driver used for PowerPC T series
SoCs,
CONFIG_BLK needs to be enabled on these platforms. It adds the SATA
controller as AHCI device, which is strictly speaking not correct,
as the controller is not AHCI compatible, But the U-Boot AHCI uclass
interface enables the usage of this DM driver,
Also fix below warning while PowerPC T series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.
Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
add socrates device tree from linux:
commit 71ae5fc87c34 ("Merge tag 'linux-kselftest-5.2-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest")
and added SPDX license identifier.
Did not fix checkpatch warnings:
arch/powerpc/dts/socrates.dts:235: check: Please don't use multiple blank lines
arch/powerpc/dts/socrates.dts:238: error: code indent should use tabs where possible
Also, add me as board maintainer.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add CONFIG_RESET_VECTOR_ADDRESS definition with the default value
in u-boot.dtsi to fix the build error below. In the configuration
header file of some MPC85xx boards, there is not the definition
of CONFIG_RESET_VECTOR_ADDRESS, while CONFIG_SYS_MPC85XX_NO_RESETVEC
is also not defined. In this case, it will lack of definition of
CONFIG_RESET_VECTOR_ADDRESS in u-boot.dtsi, and the address
0xfffffffc will be used as the boot page by default.
Error log:
DTC arch/powerpc/dts/mpc8548cds.dtb
DTC arch/powerpc/dts/mpc8548cds_36b.dtb
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds_36b.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds_36b.dtb] Error 1
dts/Makefile:38: recipe for target 'arch-dtbs' failed
make[1]: *** [arch-dtbs] Error 2
Makefile:1038: recipe for target 'dts/dt.dtb' failed
make: *** [dts/dt.dtb] Error 2
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P5040DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P4080DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P3041DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T1042D4RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T4240RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T2080RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This header file is now only used by files that access internal
environment features. Drop it from various places where it is not needed.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
As preparation for the upcoming transferring of configurations from header
files to Kconfig, a common Kconfig file for all KM boards was created. For
the moment, it only sources the other three, more specific, Kconfig files.
Therefore, the architecture Kconfig files now include the common Kconfig
file. Also, the configuration selection for KM boards was moved from the
architecture Kconfig files to the board specific Kconfig files.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Stefan Roese <sr@denx.de>
T2080 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT
and DM_PCI are not enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Use the Kconfig option to select the PCIe reset errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Use the Kconfig option to select the PCIe ASPM errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 2x 10/100 Mbit/s Ethernet (optional)
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Add a U-Boot specific dts file, which encapsulates the needed
modifications to the Gazerbeam Linux device tree.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
To support OF_EMBED, the MPC83xx architecture has to define the "_end"
symbol to correctly access the appended DT.
Fortunately, MPC8xx already defines the symbol, and the linker script is
quite similar to that of MPC83xx, so copy this approach for MPC83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Lots of stuff in processor.h was taken verbatim from the Linux kernel.
It was never synced, so most of it was removed or changed in the kernel
since it was imported.
Remove all the stuff that is unused in the current U-Boot sources;
should anybody feel the need to re-sync with the kernel, they can do it
later on.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
For a lot of inline assembly calls in the mpc8xxx and mpc83xx
directories, we already have convenient pre-defined helper functions,
but they're not used, resulting in hard-to-read code.
Use these helper functions where ever possible and useful.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
ppcDWstore/ppcDWload are hardly used by any board, but since they're
implemented in start.S, they're always present in every U-Boot image,
even if they're not needed.
Re-implement these fuctions in C with inline assembly, so that the
compiler can decide when to actually include them.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx,
but it needs some additional definitions.
Add a clock.h file, so we can use the driver for MPC83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
