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powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig

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Use the Kconfig option to select the PCIe reset errata.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-05-23 11:52:44 +08:00 committed by Prabhakar Kushwaha
parent c16dfd016a
commit 2b12f6cfe6
21 changed files with 21 additions and 20 deletions
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21
arch/powerpc/cpu/mpc85xx/Kconfig
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@ -533,6 +533,7 @@ config ARCH_BSC9132
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_IFC_A002769
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -551,6 +552,7 @@ config ARCH_C29X
select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -566,6 +568,7 @@ config ARCH_MPC8536
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@ -594,6 +597,7 @@ config ARCH_MPC8544
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -609,6 +613,7 @@ config ARCH_MPC8548
select SYS_FSL_ERRATUM_NMG_LBC103
select SYS_FSL_ERRATUM_NMG_ETSEC129
select SYS_FSL_ERRATUM_I2C_A004447
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
@ -633,6 +638,7 @@ config ARCH_MPC8560
config ARCH_MPC8568
bool
select FSL_LAW
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -643,6 +649,7 @@ config ARCH_MPC8569
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -657,6 +664,7 @@ config ARCH_MPC8572
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_DDR_115
select SYS_FSL_ERRATUM_DDR111_DDR134
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@ -681,6 +689,7 @@ config ARCH_P1010
select SYS_FSL_ERRATUM_P1010_A003549
select SYS_FSL_ERRATUM_SEC_A003571
select SYS_FSL_ERRATUM_IFC_A003399
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -718,6 +727,7 @@ config ARCH_P1020
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -738,6 +748,7 @@ config ARCH_P1021
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -759,6 +770,7 @@ config ARCH_P1022
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -772,6 +784,7 @@ config ARCH_P1023
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_I2C_A004447
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -786,6 +799,7 @@ config ARCH_P1024
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -807,6 +821,7 @@ config ARCH_P1025
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -824,6 +839,7 @@ config ARCH_P2020
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -1079,6 +1095,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@ -1101,6 +1118,7 @@ config ARCH_T2081
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@ -1437,6 +1455,9 @@ config SYS_P4080_ERRATUM_SERDES_A005
config FSL_PCIE_DISABLE_ASPM
bool
config FSL_PCIE_RESET
bool
config SYS_FSL_QORIQ_CHASSIS1
bool

1
include/configs/BSC9132QDS.h
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@ -57,7 +57,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/C29XPCIE.h
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@ -66,7 +66,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/MPC8536DS.h
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@ -36,7 +36,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */

1
include/configs/MPC8544DS.h
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@ -16,7 +16,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8548CDS.h
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@ -20,7 +20,6 @@
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8568MDS.h
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@ -16,7 +16,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8569MDS.h
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@ -15,7 +15,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8572DS.h
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@ -27,7 +27,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/P1010RDB.h
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@ -115,7 +115,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/P1022DS.h
View File

@ -81,7 +81,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/P1023RDB.h
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@ -24,7 +24,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifndef __ASSEMBLY__

1
include/configs/T208xQDS.h
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@ -491,7 +491,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */

1
include/configs/T208xRDB.h
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@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif

1
include/configs/UCP1020.h
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@ -17,7 +17,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_TARTGET_UCP1020T1)

1
include/configs/controlcenterd.h
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@ -204,7 +204,6 @@
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT

1
include/configs/p1_p2_rdb_pc.h
View File

@ -209,7 +209,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/p1_twr.h
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@ -34,7 +34,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/sbc8548.h
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@ -49,7 +49,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#ifdef CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_ENV_OVERWRITE

1
include/configs/xpedite537x.h
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@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config

1
include/configs/xpedite550x.h
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@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config