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Merge tag 'mmc-11-27-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc

Browse Source 
- fsl_esdhc update and some cleanup in ls1021a/mpc83xx code
- mmc tmio sdhi update for hs400
This commit is contained in:
Tom Rini 2019-11-28 07:33:45 -05:00
commit 089612da33
13 changed files with 268 additions and 183 deletions
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2
arch/arm/cpu/armv7/ls102xa/clock.c
View File

@ -109,8 +109,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0) / 2;
case MXC_ESDHC_CLK:
return get_bus_freq(0);
case MXC_DSPI_CLK:
return get_bus_freq(0) / 2;
case MXC_UART_CLK:

15
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -227,16 +227,6 @@ ulong get_ddr_freq(ulong dummy)
return gd->mem_clk;
}
#ifdef CONFIG_FSL_ESDHC
int get_sdhc_freq(ulong dummy)
{
if (!gd->arch.sdhc_clk)
get_clocks();
return gd->arch.sdhc_clk;
}
#endif
int get_serial_clock(void)
{
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
@ -264,11 +254,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK:
return get_dspi_freq(0);
#ifdef CONFIG_FSL_LPUART

15
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -236,16 +236,6 @@ int get_dspi_freq(ulong dummy)
return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
}
#ifdef CONFIG_FSL_ESDHC
int get_sdhc_freq(ulong dummy)
{
if (!gd->arch.sdhc_clk)
get_clocks();
return gd->arch.sdhc_clk;
}
#endif
int get_serial_clock(void)
{
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
@ -256,11 +246,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK:
return get_dspi_freq(0);
default:

2
arch/arm/include/asm/arch-fsl-layerscape/clock.h
View File

@ -14,8 +14,6 @@ enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_BUS_CLK,
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};

1
arch/arm/include/asm/arch-ls102xa/clock.h
View File

@ -12,7 +12,6 @@
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};

22
arch/powerpc/include/asm/arch-mpc83xx/clock.h
View File

@ -1,22 +0,0 @@
/*
* (C) Copyright 2018
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_POWERPC_CLOCK_H
#define __ASM_POWERPC_CLOCK_H
/* Make fsl_esdhc driver happy */
enum mxc_clock {
MXC_ESDHC_CLK,
};
DECLARE_GLOBAL_DATA_PTR;
uint mxc_get_clock(int clk)
{
return gd->arch.sdhc_clk;
}
#endif /* __ASM_POWERPC_CLOCK_H */

15
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -12,7 +12,6 @@
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_immap.h>
#include <netdev.h>
#include <fsl_mdio.h>
@ -103,20 +102,6 @@ int dram_init(void)
return 0;
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{CONFIG_SYS_FSL_ESDHC_ADDR},
};
int board_mmc_init(bd_t *bis)
{
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{

14
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -14,7 +14,6 @@
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
@ -161,19 +160,6 @@ int dram_init(void)
return fsl_initdram();
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{CONFIG_SYS_FSL_ESDHC_ADDR},
};
int board_mmc_init(bd_t *bis)
{
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;

14
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -14,7 +14,6 @@
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_immap.h>
#include <netdev.h>
@ -233,19 +232,6 @@ int dram_init(void)
return 0;
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{CONFIG_SYS_FSL_ESDHC_ADDR},
};
int board_mmc_init(bd_t *bis)
{
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);

34
drivers/mmc/fsl_esdhc.c
View File

@ -12,7 +12,6 @@
#include <config.h>
#include <common.h>
#include <command.h>
#include <clk.h>
#include <errno.h>
#include <hwconfig.h>
#include <mmc.h>
@ -81,7 +80,6 @@ struct fsl_esdhc_plat {
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
#if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc *mmc;
@ -831,9 +829,6 @@ int fsl_esdhc_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, cfg);
}
#else /* DM_MMC */
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@ -841,7 +836,6 @@ static int fsl_esdhc_probe(struct udevice *dev)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
struct mmc *mmc;
int ret;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@ -853,30 +847,10 @@ static int fsl_esdhc_probe(struct udevice *dev)
#endif
priv->dev = dev;
if (IS_ENABLED(CONFIG_CLK)) {
/* Assigned clock already set clock */
ret = clk_get_by_name(dev, "per", &priv->per_clk);
if (ret) {
printf("Failed to get per_clk\n");
return ret;
}
ret = clk_enable(&priv->per_clk);
if (ret) {
printf("Failed to enable per_clk\n");
return ret;
}
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
} else {
#ifndef CONFIG_PPC
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
#else
priv->sdhc_clk = gd->arch.sdhc_clk;
#endif
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
}
priv->sdhc_clk = gd->arch.sdhc_clk;
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
}
fsl_esdhc_get_cfg_common(priv, &plat->cfg);

311
drivers/mmc/renesas-sdhi.c
View File

@ -34,7 +34,12 @@
#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ 0x814
#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
#define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
@ -58,6 +63,49 @@
#define RENESAS_SDHI_MAX_TAP 3
#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
{ 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
};
static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
};
static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
{ 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
};
static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
{ 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
};
static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
};
static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
{
/* On R-Car Gen3, MMC0 is at 0xee140000 */
return (uintptr_t)(priv->regbase) == 0xee140000;
}
static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
{
/* read mode */
@ -87,6 +135,102 @@ static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
}
static bool renesas_sdhi_check_scc_error(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc *mmc = mmc_get_mmc_dev(dev);
unsigned long new_tap = priv->tap_set;
unsigned long error_tap = priv->tap_set;
u32 reg, smpcmp;
if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
(mmc->selected_mode != UHS_SDR104) &&
(mmc->selected_mode != MMC_HS_200) &&
(mmc->selected_mode != MMC_HS_400) &&
(priv->nrtaps != 4))
return false;
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
/* Handle automatic tuning correction */
if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
return true;
}
return false;
}
/* Handle manual tuning correction */
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
if (!reg) /* No error */
return false;
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
if (mmc->selected_mode == MMC_HS_400) {
/*
* Correction Error Status contains CMD and DAT signal status.
* In HS400, DAT signal based on DS signal, not CLK.
* Therefore, use only CMD status.
*/
smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
switch (smpcmp) {
case 0:
return false; /* No error in CMD signal */
case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
new_tap = (priv->tap_set +
priv->tap_num + 1) % priv->tap_num;
error_tap = (priv->tap_set +
priv->tap_num - 1) % priv->tap_num;
break;
case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
new_tap = (priv->tap_set +
priv->tap_num - 1) % priv->tap_num;
error_tap = (priv->tap_set +
priv->tap_num + 1) % priv->tap_num;
break;
default:
return true; /* Need re-tune */
}
if (priv->hs400_bad_tap & BIT(new_tap)) {
/*
* New tap is bad tap (cannot change).
* Compare with HS200 tuning result.
* In HS200 tuning, when smpcmp[error_tap]
* is OK, retune is executed.
*/
if (priv->smpcmp & BIT(error_tap))
return true; /* Need retune */
return false; /* cannot change */
}
priv->tap_set = new_tap;
} else {
if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
return true; /* Need re-tune */
else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
priv->tap_set = (priv->tap_set +
priv->tap_num + 1) % priv->tap_num;
else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
priv->tap_set = (priv->tap_set +
priv->tap_num - 1) % priv->tap_num;
else
return false;
}
/* Set TAP position */
tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
RENESAS_SDHI_SCC_TAPSET);
return false;
}
static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
{
u32 calib_code;
@ -97,28 +241,30 @@ static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
if (!priv->needs_adjust_hs400)
return;
if (!priv->adjust_hs400_calib_table)
return;
/*
* Enabled Manual adjust HS400 mode
*
* 1) Disabled Write Protect
* W(addr=0x00, WP_DISABLE_CODE)
* 2) Read Calibration code and adjust
* R(addr=0x26) - adjust value
* 3) Enabled Manual Calibration
*
* 2) Read Calibration code
* read_value = R(addr=0x26)
* 3) Refer to calibration table
* Calibration code = table[read_value]
* 4) Enabled Manual Calibration
* W(addr=0x22, manual mode | Calibration code)
* 4) Set Offset value to TMPPORT3 Reg
* 5) Set Offset value to TMPPORT3 Reg
*/
sd_scc_tmpport_write32(priv, 0x00,
RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
calib_code = sd_scc_tmpport_read32(priv, 0x26);
calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
if (calib_code > priv->adjust_hs400_calibrate)
calib_code -= priv->adjust_hs400_calibrate;
else
calib_code = 0;
sd_scc_tmpport_write32(priv, 0x22,
RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
calib_code);
priv->adjust_hs400_calib_table[calib_code]);
tmio_sd_writel(priv, priv->adjust_hs400_offset,
RENESAS_SDHI_SCC_TMPPORT3);
@ -220,6 +366,7 @@ static int renesas_sdhi_hs400(struct udevice *dev)
struct mmc *mmc = mmc_get_mmc_dev(dev);
bool hs400 = (mmc->selected_mode == MMC_HS_400);
int ret, taps = hs400 ? priv->nrtaps : 8;
unsigned long new_tap;
u32 reg;
if (taps == 4) /* HS400 on 4tap SoC needs different clock */
@ -229,7 +376,9 @@ static int renesas_sdhi_hs400(struct udevice *dev)
if (ret < 0)
return ret;
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
if (hs400) {
@ -250,24 +399,38 @@ static int renesas_sdhi_hs400(struct udevice *dev)
RENESAS_SDHI_SCC_DTCNTL_TAPEN,
RENESAS_SDHI_SCC_DTCNTL);
if (taps == 4) {
tmio_sd_writel(priv, priv->tap_set >> 1,
RENESAS_SDHI_SCC_TAPSET);
} else {
/* Avoid bad TAP */
if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
new_tap = (priv->tap_set +
priv->tap_num + 1) % priv->tap_num;
if (priv->hs400_bad_tap & BIT(new_tap))
new_tap = (priv->tap_set +
priv->tap_num - 1) % priv->tap_num;
if (priv->hs400_bad_tap & BIT(new_tap)) {
new_tap = priv->tap_set;
debug("Three consecutive bad tap is prohibited\n");
}
priv->tap_set = new_tap;
tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
}
tmio_sd_writel(priv, hs400 ? 0x704 : 0x300,
RENESAS_SDHI_SCC_DT2FF);
if (taps == 4) {
tmio_sd_writel(priv, priv->tap_set >> 1,
RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
RENESAS_SDHI_SCC_DT2FF);
} else {
tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
}
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
/* Execute adjust hs400 offset after setting to HS400 mode */
if (hs400)
priv->needs_adjust_hs400 = true;
@ -289,8 +452,7 @@ static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
}
static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
unsigned int tap_num, unsigned int taps,
unsigned int smpcmp)
unsigned int taps)
{
unsigned long tap_cnt; /* counter of tuning success */
unsigned long tap_start;/* start position of tuning success */
@ -307,14 +469,14 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
/* Merge the results */
for (i = 0; i < tap_num * 2; i++) {
for (i = 0; i < priv->tap_num * 2; i++) {
if (!(taps & BIT(i))) {
taps &= ~BIT(i % tap_num);
taps &= ~BIT((i % tap_num) + tap_num);
taps &= ~BIT(i % priv->tap_num);
taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
}
if (!(smpcmp & BIT(i))) {
smpcmp &= ~BIT(i % tap_num);
smpcmp &= ~BIT((i % tap_num) + tap_num);
if (!(priv->smpcmp & BIT(i))) {
priv->smpcmp &= ~BIT(i % priv->tap_num);
priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
}
}
@ -327,7 +489,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
ntap = 0;
tap_start = 0;
tap_end = 0;
for (i = 0; i < tap_num * 2; i++) {
for (i = 0; i < priv->tap_num * 2; i++) {
if (taps & BIT(i))
ntap++;
else {
@ -350,13 +512,13 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
* If all of the TAP is OK, the sampling clock position is selected by
* identifying the change point of data.
*/
if (tap_cnt == tap_num * 2) {
if (tap_cnt == priv->tap_num * 2) {
match_cnt = 0;
ntap = 0;
tap_start = 0;
tap_end = 0;
for (i = 0; i < tap_num * 2; i++) {
if (smpcmp & BIT(i))
for (i = 0; i < priv->tap_num * 2; i++) {
if (priv->smpcmp & BIT(i))
ntap++;
else {
if (ntap > match_cnt) {
@ -378,7 +540,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
select = true;
if (select)
priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
else
return -EIO;
@ -399,7 +561,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
unsigned int tap_num;
unsigned int taps = 0, smpcmp = 0;
unsigned int taps = 0;
int i, ret = 0;
u32 caps;
@ -419,15 +581,19 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
/* Tuning is not supported */
goto out;
if (tap_num * 2 >= sizeof(taps) * 8) {
priv->tap_num = tap_num;
if (priv->tap_num * 2 >= sizeof(taps) * 8) {
dev_err(dev,
"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
goto out;
}
priv->smpcmp = 0;
/* Issue CMD19 twice for each tap */
for (i = 0; i < 2 * tap_num; i++) {
renesas_sdhi_prepare_tuning(priv, i % tap_num);
for (i = 0; i < 2 * priv->tap_num; i++) {
renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
/* Force PIO for the tuning */
caps = priv->caps;
@ -442,12 +608,12 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
ret = renesas_sdhi_compare_scc_data(priv);
if (ret == 0)
smpcmp |= BIT(i);
priv->smpcmp |= BIT(i);
mdelay(1);
}
ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
ret = renesas_sdhi_select_tuning(priv, taps);
out:
if (ret < 0) {
@ -535,6 +701,8 @@ static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_priv *priv = dev_get_priv(dev);
renesas_sdhi_check_scc_error(dev);
if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
renesas_sdhi_adjust_hs400_mode_enable(priv);
#endif
@ -582,50 +750,89 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
static void renesas_sdhi_filter_caps(struct udevice *dev)
{
struct tmio_sd_plat *plat = dev_get_platdata(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
return;
/* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_platdata(dev);
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() <= 2)))
(rmobile_get_cpu_rev_fraction() < 2)))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
/* M3W ES1.x for x>2 can use HS400 with manual adjustment */
/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() >= 2)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() == 2)) ||
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
/* H3 ES3.0 can use HS400 with manual adjustment */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() >= 3)) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 0;
priv->adjust_hs400_calib_table =
r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* M3W ES1.2 can use HS400 with manual adjustment */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() == 2)) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() > 2)) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 0;
priv->adjust_hs400_calibrate = 0x9;
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
priv->adjust_hs400_calib_table =
r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* M3N can use HS400 with manual adjustment */
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 0;
priv->adjust_hs400_calibrate = 0x0;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* E3 can use HS400 with manual adjustment */
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 0;
priv->adjust_hs400_calibrate = 0x2;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* H3 ES2.0 uses 4 tuning taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() == 2))
/* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 2)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() <= 2)))
priv->nrtaps = 4;
else
priv->nrtaps = 8;
#endif
/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||

2
drivers/mmc/sdhci.c
View File

@ -660,7 +660,7 @@ int sdhci_probe(struct udevice *dev)
return sdhci_init(mmc);
}
int sdhci_get_cd(struct udevice *dev)
static int sdhci_get_cd(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct sdhci_host *host = mmc->priv;

4
drivers/mmc/tmio-common.h
View File

@ -137,12 +137,16 @@ struct tmio_sd_priv {
struct clk clk;
#endif
#if CONFIG_IS_ENABLED(RENESAS_SDHI)
unsigned int smpcmp;
u8 tap_set;
u8 tap_num;
u8 nrtaps;
bool needs_adjust_hs400;
bool adjust_hs400_enable;
u8 adjust_hs400_offset;
u8 adjust_hs400_calibrate;
u8 hs400_bad_tap;
const u8 *adjust_hs400_calib_table;
#endif
ulong (*clk_get_rate)(struct tmio_sd_priv *);
};