Commit Graph

30771 Commits

Author SHA1 Message Date
Tom Rini
b48b69ba10 Merge git://git.denx.de/u-boot-marvell 2015-06-15 10:57:29 -04:00
Tom Rini
08520bf5e4 omap5: Exclude more environment from SPL builds
In the cases where we make use of environment in SPL we do not need
these defaults compiled in and available.  These are taking up space
that in some cases now prevent linking, so drop.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:28 -04:00
Yegor Yefremov
6ce8932494 board: add support for Vision System's Baltos Industrial PC
Vision Systems's Baltos is based on AM335x SoC
from Texas Instruments. This patch adds support
such Industrial PCs in mainline u-boot.

[ balbi@ti.com: updated original patch to current u-boot ]

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-06-15 10:57:28 -04:00
Lokesh Vutla
c997da5c53 ARM: DRA7: emif: Fix DDR init sequence during warm reset
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-15 10:57:27 -04:00
Masahiro Yamada
2ce6ecacca avr32: move CONFIG_SYS_GENERIC_BOARD to Kconfig
Now all the AVR32 boards have been converted into Generic Board.
Select it in Kconfig and clean up defines in header files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-06-15 10:57:27 -04:00
Lokesh Vutla
42da5adfca ARM: AM43x: Fix MAX_RAM_BANK_SIZE
On AM437x-GP Evm there is 2GB of DDR3 memory available as stated in
AM437x GP EVM HardwareUser's guide http://www.ti.com/lit/ug/spruhw7/spruhw7.pdf.
But MAX_RAM_BANK_SIZE is defined as 1GB.
Fixing MAX_RAM_BANK_SIZE to 2GB on AM43xx.

Reported-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:27 -04:00
Tom Rini
7c352cd38d am33xx: Re-enable SW levelling for DDR2
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet.  In other cases
update the call to be as functional as before and check an already
programmed value in.

Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-15 10:57:26 -04:00
Lokesh Vutla
37be54fd13 ARM: BeagleBoard-x15: Enable i2c5 clocks
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:26 -04:00
Tom Rini
0ad5eaa4e5 am43xx_evm: Enable NAND boot
Enable booting from NAND on the am437xx-evm.

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:26 -04:00
Roger Quadros
cda6017629 am335x_evm: nand: Fix boot from NAND
Use the correct partition names from with the Device Tree blob
and the kernel is picked up. Also use partition name instead of
number for the root filesystem in the kernel boot arguments.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:26 -04:00
Roger Quadros
9ddef489c4 am335x_evm: am44xx_evm: dra7xx_evm: nand: Fix file-system partition name
We almost always use UBIFS for user accessible NAND file systems and
the UBIFS file system might contain more than one volume within the
single NAND partition. The last NAND partition is therefore more
appropriately named as "NAND.file-system" instead of "NAND.rootfs"

The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the
last NAND partition. This patch makes the partition name consistent
between u-boot and the kernel.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:25 -04:00
Roger Quadros
ab16817cfb configs: am43xx_evm: Enable NAND
AM43xx EVMs have NAND so enable it.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:25 -04:00
Mark Langsdorf
ef51c416bc highbank: add custom ahci_link_up function
The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
so override ahci_link_up with custom function to handle combophy setup.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Richard Gibbs
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
2015-06-15 10:57:25 -04:00
Stefan Roese
1c0df9ef6e tools/kwboot: Add parameters to set delay and timeout via cmdline
To support the Armada 38x, new values for the request-delay and the
response-timeout are needed. As the values already implemented in
this tool (for Kirkwood and Armada XP) don't seem to work here.
To make this more flexible, lets add make those 2 parameters
configurable via the cmdline. Here the new parameters:

-q <req-delay>:  use specific request-delay
-s <resp-timeo>: use specific response-timeout

For the Marvell DB-88F6820 these values are known to work:

One board:
-q 2 -s 1

2nd board:
-q 5 -s 5

So this seems to be even board specific. But with this patch now
those values can be specified and tested via the cmdline.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-06-14 17:48:28 +02:00
Kevin Smith
e1b078e06c arm: mvebu: Update CBAR with SOC regs base
SMP-enabled Linux kernels read the CBAR register in CP15 to find
the address of the SCU registers.  After remapping internal
registers, also update the CBAR so the kernel can find them.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
2015-06-14 17:48:28 +02:00
Stefan Roese
5730360efc arm: mvebu: Disable L2 cache before enabling d-cache
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
2015-06-14 17:48:28 +02:00
Kevin Smith
a0aad12346 tools/kwbimage.c: Correct header size for SPI boot
If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board
to specify the offset of the payload image into the kwb image
file.  This value was being used to locate the image, but was not
used in the "header size" field of the main header.  Move the
use of this macro into the function that returns the header size
so that the same value is used in all places.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Stefan Roese <sr@denx.de>
2015-06-14 17:48:28 +02:00
Mark Langsdorf
f8b009e8b7 ahci: extend data io wait to 10s
The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
2015-06-12 16:53:04 -04:00
Mark Langsdorf
2b42c9317d ahci: support LBA48 data reads for 2+TB drives
Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.

This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI controller.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
[trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop
 warnings on platforms that don't enable that feature ]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-12 16:52:32 -04:00
Mark Langsdorf
35df893199 cmd_scsi: use lbaint_t for LBA values instead of u32
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
2015-06-12 13:02:07 -04:00
Mark Langsdorf
f8973325d0 ARM: highbank: add reset support for Calxeda Midway machine
The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.

Andre: rework detection of Highbank vs. Midway
Rob: fix Andre's reworked detection

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Rob Herring <robh@kernel.org>
2015-06-12 13:02:07 -04:00
Rob Herring
083ffd65cb ARM: highbank: add missing SCU register setup for reset
Andre: assign names to the magic values

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
2015-06-12 13:02:07 -04:00
Lokesh Vutla
8f6c80b966 ARM: BeagleBoard-x15: Add mux data
Adding the mux data, manual and virtual mode
settings for BeagleBoard-X15.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
2015-06-12 13:02:07 -04:00
Lokesh Vutla
f91e0c4c77 ARM: BeagleBoard-x15: Enable IO delay recalibration sequence
Enable IO delay recalibration sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:06 -04:00
Lokesh Vutla
2cb3cccb8b ARM: DRA7: CPSW: Remove IO delay hack
Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-12 13:02:06 -04:00
Nishanth Menon
27d170af17 ARM: DRA7-evm: Add mux data
Adding the mux data, manual and virtual mode
settings for DRA7-evm.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2015-06-12 13:02:06 -04:00
Lokesh Vutla
706dd34893 ARM: DRA7-evm: Enable IO delay recalibration sequence
Enabling IO delay recalibration sequence for DRA7 EVM.
UART and I2C are configured before IO delay recalibration sequence
as these are used earlier and safe to use.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:06 -04:00
Lokesh Vutla
71bed1855f ARM: DRA7: Add support for manual mode configuration
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.

struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
  And pass the offset of the CFG_XXX register in iodelay_cfg_entry.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
eda6fbcc8c ARM: DRA7: Add support for IO delay configuration
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.

IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
61d383d0f7 ARM: DRA7: Add support for virtual mode configuration
In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.

Provide easy to use macro to do the same.

For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
  CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
6ae4c3efbd ARM: DRA7: Add pinctrl register definitions
Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
1f68451ca0 ARM: DRA7: Make do_set_mux32() generic
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
ee4dc2590f ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-12 12:43:07 -04:00
Lokesh Vutla
536d874708 ARM: DRA7: Update DDR IO registers
Update DDR IO register values.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:07 -04:00
Lokesh Vutla
a5c5c5b500 ARM: DRA7: Update DDR IO configuration
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
c7400e4882 ARM: DRA7: Add is_dra72x cpu check definition
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
f308b4fce5 ARM: DRA72-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
920638fa5e ARM: DRA7-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
496edffdb2 ARM: BeagleBoard-X15: Enable HW leveling
Updating EMIF registers to enable HW leveling
on BeagleBoard-X15.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
6213db78f4 ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Masahiro Yamada
9d01b7872e kconfiglib: sync with the latest in Kconfiglib project
This commit imports some updates of kconfiglib.py from
https://github.com/ulfalizer/Kconfiglib

 - Warn about and ignore the "allnoconfig_y" Kconfig option
 - Statements in choices inherit menu/if deps
 - Add Symbol.is_allnoconfig_y()
 - Hint that modules are still supported despite warnings.
 - Add warning related to get_defconfig_filename().
 - Fix typo in docs.
 - Allow digits in $-references to symbols.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Signed-off-by: Philip Craig <philipjcraig@gmail.com>
Signed-off-by: Jakub Sitnicki <jsitnicki@gmail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-06-12 12:43:06 -04:00
Pali Rohár
64d16706a0 Nokia RX-51: Fix calculating return address in save_boot_params
Commit e11c6c279d broke calculating lr register
in function save_boot_params() and caused U-Boot to crash at early boot time
on Nokia N900 board.

This patch fix calculating return address in lr register and make Nokia N900
board bootable again. Patch was tested in qemu and also on real N900 HW.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
2015-06-12 08:11:18 -04:00
Tom Rini
b9130d88fa Merge git://git.denx.de/u-boot-dm 2015-06-11 21:18:52 -04:00
Hannes Schmelzer
7bb7d672aa common/cmd_bdinfo: show gd->board_type
sometimes it is usefull to know if board-detection has
written the correct value into gd->board_type.

For this we add some output to the bdinfo command.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2015-06-11 08:29:14 -04:00
Masahiro Yamada
3850dbe833 blackfin: fix undefined reference to srand and rand
Commit 9ba9e85f3f (net: Fix NET_RANDOM_ETHADDR dependencies)
accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f3f should not have
touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
header files, which caused undefined reference to srand and rand.
CONFIG_LIB_RAND=y must be revived for such boards.

BTW, this commit indeed makes it better, but even with this fix,
three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
build due to region 'ram' overflowed error.  This was cause by
commit 6eed3786c6 (net: Move the CMD_NET config to defconfigs)
because CMD_NET selects NET, and NET selects REGEX.  Eventually,
some boards were newly enabled with CONFIG_REGEX, increasing the
memory footprint.  A patch is expected to fix the build error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-06-11 08:28:35 -04:00
Masahiro Yamada
0592115d47 README.scrapyard: add entries for dead AVR32 boards
Some AVR32 boards were dropped by the following commits:
 9eb45aabe0 (avr32: delete non generic board favr-32-ezkit)
 e369307644 (avr32: delete non generic board hammerhead)
 c62d2f8fc5 (avr32: delete non generic board mimc200)
 e5354b8a9e (avr32: delete non generic board's atstk100{3, 4, 6})

Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-06-11 08:27:26 -04:00
Tom Rini
815f574fcf Merge branch 'master' of http://git.denx.de/u-boot-samsung 2015-06-10 21:45:51 -04:00
Simon Glass
257bfd2e21 dm: usb: tegra: Drop legacy USB code
Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Simon Glass
af28224546 sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Simon Glass
a59abd1049 Remove SPL undefine of CONFIG_OF_CONTROL
Allow SPL to be built with this option so that we can support device tree
control. Disable the simple bus for now in SPL. It may be needed later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00