mirror of
https://github.com/brain-hackers/u-boot-brain
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avr32: delete non generic board mimc200
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Andreas Bießmann
parent
e369307644
commit
c62d2f8fc5
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@ -29,15 +29,11 @@ config TARGET_ATSTK1006
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config TARGET_GRASSHOPPER
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bool "Support grasshopper"
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config TARGET_MIMC200
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bool "Support mimc200"
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endchoice
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source "board/atmel/atngw100/Kconfig"
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source "board/atmel/atngw100mkii/Kconfig"
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source "board/atmel/atstk1000/Kconfig"
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source "board/in-circuit/grasshopper/Kconfig"
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source "board/mimc/mimc200/Kconfig"
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endmenu
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@ -1,15 +0,0 @@
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if TARGET_MIMC200
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config SYS_BOARD
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default "mimc200"
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config SYS_VENDOR
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default "mimc"
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config SYS_SOC
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default "at32ap700x"
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config SYS_CONFIG_NAME
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default "mimc200"
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endif
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@ -1,6 +0,0 @@
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MIMC200 BOARD
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M: Mark Jackson <mpfj@mimc.co.uk>
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S: Maintained
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F: board/mimc/mimc200/
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F: include/configs/mimc200.h
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F: configs/mimc200_defconfig
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@ -1,6 +0,0 @@
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#
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# Copyright (C) 2005-2006 Atmel Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := mimc200.o
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@ -1,197 +0,0 @@
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/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/portmux.h>
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#include <atmel_lcdc.h>
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#include <lcd.h>
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#include "../../../arch/avr32/cpu/hsmc3.h"
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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{
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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.virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
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.phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_WRBACK,
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},
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};
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#if defined(CONFIG_LCD)
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/* 480x272x16 @ 72 Hz */
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vidinfo_t panel_info = {
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.vl_col = 480, /* Number of columns */
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.vl_row = 272, /* Number of rows */
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.vl_clk = 5000000, /* pixel clock in ps */
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.vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
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ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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.vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
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.vl_tft = 1, /* 0 = passive, 1 = TFT */
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.vl_hsync_len = 42, /* Length of horizontal sync */
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.vl_left_margin = 1, /* Time from sync to picture */
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.vl_right_margin = 1, /* Time from picture to sync */
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.vl_vsync_len = 1, /* Length of vertical sync */
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.vl_upper_margin = 12, /* Time from sync to picture */
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.vl_lower_margin = 1, /* Time from picture to sync */
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.mmio = LCDC_BASE, /* Memory mapped registers */
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};
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void lcd_enable(void)
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{
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}
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void lcd_disable(void)
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{
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}
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_16BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 6,
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.trp = 2,
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.trcd = 2,
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.tras = 6,
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.txsr = 6,
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/* 15.6 us */
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
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};
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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/* Enable 26 address bits and NCS2 */
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portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
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sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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/* de-assert "force sys reset" pin */
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portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
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/* init custom i/o */
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/* cpu type inputs */
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portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
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PORTMUX_DIR_INPUT);
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/* main board type inputs */
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portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
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PORTMUX_DIR_INPUT);
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/* DEBUG input (use weak pullup) */
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
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PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
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/* are we suppressing the console ? */
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if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
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gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
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/* reset phys */
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
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portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
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udelay(5000);
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/* release phys reset */
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gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
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/* setup Data Flash chip select (NCS2) */
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hsmc3_writel(MODE2, 0x20121003);
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hsmc3_writel(CYCLE2, 0x000a0009);
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hsmc3_writel(PULSE2, 0x0a060806);
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hsmc3_writel(SETUP2, 0x00030102);
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/* setup FRAM chip select (NCS3) */
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hsmc3_writel(MODE3, 0x10120001);
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hsmc3_writel(CYCLE3, 0x001e001d);
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hsmc3_writel(PULSE3, 0x08040704);
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hsmc3_writel(SETUP3, 0x02050204);
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#if defined(CONFIG_MACB)
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/* init macb0 pins */
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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#if defined(CONFIG_LCD)
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portmux_enable_lcdc(1);
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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return 0;
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}
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int board_postclk_init(void)
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{
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/* Use GCLK0 as 10MHz output */
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gclk_enable_output(0, PORTMUX_DRIVE_LOW);
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gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
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return 0;
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}
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return (bus == 0) && (cs == 0);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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#endif /* CONFIG_ATMEL_SPI */
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bi)
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{
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macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
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macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
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return 0;
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}
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#endif
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@ -1,3 +0,0 @@
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CONFIG_AVR32=y
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CONFIG_TARGET_MIMC200=y
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CONFIG_CMD_NET=y
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@ -1,176 +0,0 @@
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/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Configuration settings for the AVR32 Network Gateway
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_MIMC200
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#define CONFIG_MIMC200_EXT_FLASH
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
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* and the PBA bus to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 10000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 15
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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#define CONFIG_SYS_CLKDIV_CPU 0
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#define CONFIG_SYS_CLKDIV_HSB 1
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#define CONFIG_SYS_CLKDIV_PBA 2
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM, NOR flash and FRAM */
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#define CONFIG_SYS_NR_VM_REGIONS 3
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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#define CONFIG_MIMC200_DBGLINK 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
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#define CONFIG_BOOTCOMMAND \
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"fsload boot/uImage; bootm"
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#define CONFIG_SILENT_CONSOLE /* enable silent startup */
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#define CONFIG_DISABLE_CONSOLE /* disable console */
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#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */
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#define CONFIG_LCD 1
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_AUTOBOOT
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/*
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* After booting the board for the first time, new ethernet addresses
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* should be generated and assigned to the environment variables
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* "ethaddr" and "eth1addr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* BOOTP/DHCP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#if defined(CONFIG_LCD)
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#define CONFIG_CMD_BMP
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#define CONFIG_ATMEL_LCD 1
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#define LCD_BPP LCD_COLOR16
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#define CONFIG_BMP_16BPP 1
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#define CONFIG_FB_ADDR 0x10600000
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#define CONFIG_WHITE_ON_BLACK 1
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#define CONFIG_VIDEO_BMP_GZIP 1
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
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#define CONFIG_ATMEL_LCD_BGR555 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_SPLASH_SCREEN 1
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#endif
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_SYS_FRAM_BASE 0x08000000
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#define CONFIG_SYS_FRAM_SIZE 0x20000
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (1024*1024)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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