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ARM: DRA7: emif: Fix DDR init sequence during warm reset

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Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2015-06-04 10:08:50 +05:30 committed by Tom Rini
parent 2ce6ecacca
commit c997da5c53
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv7/omap-common/emif-common.c
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@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base)
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
if (!in_sdram && (!warm_reset() || is_dra7xx())) {
if (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base)
ddr3_init(base, regs);
}
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_DDR3)) {
EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
omap5_ddr3_leveling(base, regs);