Commit Graph

6184 Commits

Author SHA1 Message Date
Hans de Goede
e976b868f2 videomodes: Add video_get_ctfb_res_modes helper function
Add a video_get_ctfb_res_modes() helper function, which uses
video_get_video_mode() to parse the 'video-mode' environment variable and then
looks up the matching mode in res_mode_init and returns the matching mode.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
59bb610922 videomodes: Add a bunch of high res modes
Add modes useful for hd-tvs and modern monitors.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
92a88c33f0 videomodes: Add (vesa) standard timings
The timings for the modes defined in videomodes.c differ (significantly)
from vesa standard timings for these modes.

This commit adds a version with the proper std timings for these modes,
since I do not want to cause regressions, boards which want to use the standard
timings need to define CONFIG_VIDEO_STD_TIMINGS to get the new correct timings.

Since there is no std timing for 960x720 this commit uses the timing used
by the nvidia video drivers for 960x720, which uses a standard pixelclock
of 74.25 MHz rather then the weird 76.335... clock used by the old modes.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
0c91d25767 videomodes: Add pixelclock_khz and refresh fields to ctfb_res_modes
Add pixelclock_khz and refresh fields to ctfb_res_modes:

1) pixelclocks are usually referred to in hz, not picoseconds, and e.g
pll-s are also typically programmed in hz, not ps. Converting between the
2 leads to rounding differences, add a pixelclock_khz field to directly
store the *exact* pixelclock for a mode, so that drivers do not need to
resort to rounding tricks to try and guess the exact pixelclock;

2) The video-mode environment variable, as parsed by video_get_video_mode
also contains the vertical refresh rate, add a refresh field, so that
the refresh-rate can be matched when parsing the video-mode environment
variable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:37 +01:00
Hans de Goede
50e0d5e60b sunxi: axp221: Explicitly turn off unused voltages
Explicitly turn off unused voltages, rather then leaving them as is. Likewise
explictly enabled the dcdc convertors, rather then assuming they are already
enabled at boot.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
1262a85fe3 sunxi: axp221: Make dcdc1 voltage configurable
The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like
GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to
safe battery, but not on all, make it configurable so that we can use the
same settings as the original firmware on all boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
f70444980b sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usage
Some of the ldo-s of the axp221 are used in the same way on most boards, add
comments to the Kconfig help text to reflect this, and give them defaults
matching their typical usage.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
bdcdf84631 sunxi: axp221: Add axp223 support
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Axel Lin
b0c4ae1a51 mmc: sunxi: Fix misuse of gpio_direction_input()
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
f3fba5665b sun6i: axp221: Add axp221_get_sid function
For sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a function to retreive the sid.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
fc3a832576 sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.

The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).

For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.

This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Felipe Balbi
78fb6e3166 pmic: add tps62362 simple wrapper code
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13 15:26:10 -05:00
Daniel Mack
c316f577b4 mtd: OMAP: Enable GPMC prefetch mode
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.

The current implementation has two limitations:

 a) it only works in 8-bit mode
 b) it only supports read access

Both is easily fixable by someone who has hardware to implement it.

Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.

Tested on AM335x hardware.

Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
2015-01-13 11:51:23 -05:00
Bin Meng
ade8127a79 x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Simon Glass
9a99caf3f3 x86: pci: Display vesa modes in hex
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:25:00 -08:00
Simon Glass
fba7eac1c8 x86: video: Add debug option to time the BIOS copy
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
23609c71dc x86: pci: Don't return a vesa mode when there is not video
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Simon Glass
6dcc815984 x86: video: Add a debug() to display the frame buffer address
Provide a way to display this address when booting.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Bin Meng
1eb47efc49 x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
3db886a5bf serial: ns16550: Support ns16550 compatible pci uart devices
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.

Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
a62e84d7b1 fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13 07:24:40 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Nikita Kiryanov
f4469f50b0 lcd: remove LCD_MONOCHROME
No one is using LCD_MONOCHROME; remove related code.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-10 17:50:04 +01:00
Nikita Kiryanov
ad8a245620 mpc8xx_lcd: get rid of CONFIG_EDT32F10
No one is using CONFIG_EDT32F10; remove related code.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-10 17:49:10 +01:00
Nikita Kiryanov
dc6b5b3a15 lcd: remove CONFIG_SYS_INVERT_COLORS
No one is using CONFIG_SYS_INVERT_COLORS; remove related code.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-10 17:45:00 +01:00
Masahiro Yamada
ab37b76d5d mtd: nand: do not scan BBT after scrub
Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.

It violates the intention of NAND_SKIP_BBTSCAN.

Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.

Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub.  We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
2015-01-09 12:19:06 -06:00
Masahiro Yamada
bf80ee6e1d mtd: nand: Mark the BBT as scanned prior to calling scan_bbt again
Commit 35c204d8a9 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.

Its git-log claimed that it reinstated the change as by commit
fb49454b1b ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".

It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.

Reinstate commit ff49ea8977 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rostislav Lisovy <lisovy@merica.cz>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
2015-01-09 12:19:02 -06:00
Masahiro Yamada
756963d7da mtd: nand: revive "nand scrub" command
Since commit ff94bc40af (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
2015-01-09 12:18:58 -06:00
Tom Rini
f10d86d3ff Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-08 13:50:38 -05:00
Peng Fan
5f7f70c171 qspi:fsl implement AHB read
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.

The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB read,
we can directly memcpy, a "missed" access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr register
to initiate a read from flash device.

Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little
endian but not 32bit Little endia.

Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.
Actually if Vybrid is migrated to use AHB read, this option can be removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.

In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-09 00:03:28 +05:30
Peng Fan
c36ecf3abf i2c:mxc fix array size of i2c_data
We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3,
there are 4 i2c interface, but not 3. So the size of i2c_data array should
be calculated using "ARRAY_SIZE(i2c_bases)".

To avoid compile error, move i2c_bases before sram_data structure which
contains i2c_data array.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-08 11:00:45 -05:00
Axel Lin
78c80114b5 spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]
No functional change, just simplify the code a bit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-08 12:02:55 +05:30
Axel Lin
1dc7d00f27 spi: cadence_qspi: Fix checking return value of fdt_first_subnode()
fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.
0 is supposed to be a valid offset returns from fdt_first_subnode().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:30:54 +05:30
Peng Fan
a235878387 spi:fsl-quadspi support bank register read write
To support bigger than 16MB size qspi flashes, spi framework uses bank
switch to access higher bank or lower bank.

In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR
is initialized in LUT register with related pad and length configuration.
qspi_op_pp is originally for page programming, this patch reuses this function
for bank register switch and renamed it with qspi_op_write.

Since bank or EAR register is only 1 byte length, however original qspi_op_pp
or now renamed qspi_op_write only support 4 bytes lenght as the access unit,
this will trigger data abort exception when access EAR or bank register.
This is because upper framework passes a 1 bytes pointer to qspi_op_write,
however qspi_op_write treat it as an int pointer. This patch fixes this for
accessing EAR or bank register.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:25:05 +05:30
Tom Rini
2ed3f91143 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2015-01-06 10:44:47 -05:00
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Axel Lin
501943696e spi: designware_spi: Fix detecting FIFO depth
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
   register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
   to test fifo == 257. In the case fifo is 257, it means the latest valid
   setting is fifo = 256. So after the for loop iteration, we should check
   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 15:52:27 +05:30
Gerald Kerma
ac0b729844 MVEBUMMC : REMOVE unnecessary delay from init
Remove unnessecary delay from mvebu_mmc_initialize

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:10:28 +02:00
Gerald Kerma
02b2739e8f MVEBUMMC : CLEAN code
Clean mvebu_mmc_send_cmd

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:10:23 +02:00
Gerald Kerma
86eeecafc2 MVEBUMMC : REMOVE unnecessary delays
Remove delays in mvebu_mmc_set_bus and mvebu_mmc_set_clk

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:10:16 +02:00
Gerald Kerma
fc0f25f919 MVEBUMMC : FIX debug strings
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:10:12 +02:00
Gerald Kerma
28d27b79e3 MVEBUMMC : Speed up access time
Get about 40x faster access on SHEEVAPLUG MMC
 Fix some SD type compatibility

 Changes in v3:
 - fix the HW_STATE (from linux mvsdio)
 - review delays and timeouts

 Changes in v2:
 - increase number of loops
 - remove initial delay

 Changes in v1:
 - review all loops, delays and timeouts

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:10:04 +02:00
Gerald Kerma
2591fbdba3 MVEBUMMC : Change copyright date
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-06 10:09:45 +02:00
Tom Rini
fc078895d8 Merge branch 'misc' of git://git.denx.de/u-boot-x86 2015-01-05 20:00:25 -05:00
Sjoerd Simons
9332274989 cros-ec-keyboard: Synchronize DT binding from linux
The ChromeOS EC keyboard is used by various different chromebooks. Peach
pi being the third board in the u-boot tree to use it (snow and peach
pit the other two). Rather then embedding the same big DT node in the
peach-pi DT again, copy the dtsi snippit & bindings documentation from
linux and include it in all 3 boards.

This slightly changes the dt bindings in u-boot:
  * google,key-rows becomes keypad,num-rows
  * google,key-colums becomes keypad,num-colums
  * google,repeat-delay-ms and google,repeat-rate-ms are no longer used
    and replaced by hardcoded values (similar to tegra kbc)

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:16 -07:00
Masahiro Yamada
ee5ee87642 i2c_eeprom: include <linux/err.h> to fix build error
drivers/misc/i2c_eeprom.c fails to build unless CONFIG_FIT_SIGNATURE
is defined.

  CC      drivers/misc/i2c_eeprom.o
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:15:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:15:10: note: each undeclared identifier
is reported only once for each function it appears in
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_write':
drivers/misc/i2c_eeprom.c:21:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:22:1: warning: control reaches end of
non-void function [-Wreturn-type]
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:16:1: warning: control reaches end of
non-void function [-Wreturn-type]
make[2]: *** [drivers/misc/i2c_eeprom.o] Error 1
make[1]: *** [drivers/misc] Error 2
make: *** [drivers] Error 2

By the way, Sandbox (enabling CONFIG_FIT_SIGNATURE) is luckily
working depending on it.
Sandbox includes include/asm-generic/errno.h
            from include/errno.h
            from include/u-boot/rsa-checksum.h
            from include/image.h
            from include/common.h
            from drivers/misc/i2c_eeprom.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:15 -07:00
Guido Martínez
eb54d2c70c mtd: nand: omap_gpmc: fix error handling
"err" was an unsigned variable, causing negative error codes to turn
into positive values, which are interpreted as an amount of succesfully
corrected bitflips (and thus not an error).

In particular, this resulted in that if the elm reports uncorrectable
errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded.

Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-01-05 16:40:18 -05:00
Dmitry Lifshitz
1a33b7356a ahci-plat: provide a weak scsi_bus_reset() hook
This allow the platform to handle a custom reset sequence.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:46 -05:00
Dmitry Lifshitz
6b68888a33 ahci: introduce ahci_reset()
Extract controller reset code from ahci_host_init() into separate
ahci_reset().

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:46 -05:00
Masahiro Yamada
d622ac3927 powerpc: mpc824x: remove MPC824X cpu support
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
9067b30008 mpc8260: remove atc board support
These boards are still non-generic boards.

drivers/rtc/ds12887.c should also be removed because it can not
be built without CONFIG_ATC.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
acc2372db0 mpc8xx: remove lwmon board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
79cbecb81b mpc8xx: remove R360MPI board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
8737fc7529 mpc8xx: remove RRvision board support
This board is still a non-generic board.

Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted
because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177,
CONFIG_VIDEO_ENCODER_AD7179 are not defined any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
ceaf499b50 powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
5d2a5ef712 mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:50 -05:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Rene Griessl
e9954b867c usb: eth: add ASIX AX88179 DRIVER
This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network
adapter.

Driver has been tested on the RECS5250 COM module (similar to ARDALE5250).
Testcase was DHCP and PXE boot.

Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
2014-12-31 19:10:13 +01:00
Peng Fan
ba4dc8ab72 imx:qspi add 4K erase support
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
b93ab2ee75 arm:mx6sx add QSPI support
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
ed0c81c654 QuadSPI: use correct amba_base
According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
53e3db7f64 QuadSPI: use QSPI_CMD_xx instead of flash opcodes
Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
d8046ff0b0 Merge git://git.denx.de/u-boot-x86 2014-12-19 17:09:26 -05:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Thierry Reding
cc0856cd14 net: rtl8169: Add support for RTL-8168/8111g
This network interface card is found on the NVIDIA Jetson TK1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
d58acdcbfb net: rtl8169: Use non-cached memory if available
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
dad3ba0f0b net: rtl8169: Properly align buffers
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is higher than the
256 byte alignment requirements of the NIC.

Also add a warning if the cache-line size is larger than the descriptor
size, because the driver may discard changes to descriptors made by the
hardware when requeuing RX buffers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
c94bbfdf51 net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER
According to the top-level README file, this configuration setting can
be used to override the number of receive buffers that an ethernet NIC
uses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:21:41 -07:00
Thierry Reding
f315828b0d pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
6173c45b21 power: Add AMS AS3722 PMIC support
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Tom Rini
7a7ffedabd Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-12-18 12:37:18 -05:00
Adnan Ali
babe6994ca sf: sf_params: Add S25FL164K flash identifier info
Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:48:30 +05:30
Adnan Ali
cf156007e0 sf: sf_params: Add S25FL116K flash support
Added S25FL116K flash and tested on Marvell 88F6281 based system.

Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:45:35 +05:30
Shengzhou Liu
b45a3de086 mtd/spi: Add support for SST25WF040B
Add support for SST25WF040B-40I-SN flash.
Tested on T1024QDS board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:19:24 +05:30
Jagannadha Sutradharudu Teki
2bf48026fd mtd: sf: Zap ramtron driver
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.

Commit details for EMK zap:
"ppc/arm: zap EMK boards"
(sha1: d58a9451e7)

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
2014-12-18 18:17:54 +05:30
Przemyslaw Marczak
f597fc3d4c dfu: dfu_get_buf: check the value of env dfu_bufsiz before use
In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.

This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.

This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Przemyslaw Marczak
62a96d805f gadget: f_thor: check pointers before use in download_tail()
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Przemyslaw Marczak
7da6fa2716 dfu: mmc: check if mmc device exists in mmc_block_op()
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Rob Herring
267abc626d fastboot: add support for continue command
The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read <...>; bootm" to fully implement the fastboot continue function.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Rob Herring
fe1b28c9f0 usb, g_dnl: generalize DFU detach functions
In order to add detach functions for fastboot, make the DFU detach related
functions common so they can be shared.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:05 +01:00
Tom Rini
e3bf81b1e8 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-12-16 15:20:02 -05:00
Bo Shen
68ae882596 USB: gadget: atmel_usba_udc: fix transfer hang issue
When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-12-16 16:08:50 +01:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Tom Rini
b9206e61f3 Merge git://git.denx.de/u-boot-x86 2014-12-15 17:13:47 -05:00
Zhao Qiang
9c7c86f431 qe/deep-sleep: modify qe deep-sleep for generic board
Deep sleep for generic board is supported now, modify qe
deep-sleep code to adapt it.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:49 -08:00
gaurav rana
851c9dbad2 crypto/fsl: Fix RNG instantiation failure.
Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:26 -08:00
Shengzhou Liu
24d827f526 net/fm: update ft_fixup_port to differentiate dual-role mac
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:55 -08:00
York Sun
938bbb6013 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:12 -08:00
Bin Meng
7e7740397d x86: ich-spi: Add Intel Tunnel Creek SPI controller support
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
a2927e09bc x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
2795573a8c x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
996467172e x86: ich-spi: Set the tx operation mode for ich 7
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
fa388bca3e x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Jagannadha Sutradharudu Teki
54ba653ab6 sf: Enable byte program support
Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
74c2cee4e8 spi: sf: Support byte program for sst spi flash
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Simon Glass
b648742a17 spi: Fix flag collision for SST_WP
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.

Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Jagannadha Sutradharudu Teki
6dd6e90e13 sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported
controllers.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 15:08:04 -07:00
Simon Glass
f46f3f356f bios_emulator: Correct ordering of includes
We should include common.h before other includes. This actually causes
a build error on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Axel Lin
0a54745fc2 gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Bin Meng
15c7c6b31a x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Tom Rini
6983951a61 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-12-12 15:02:00 -05:00
Andrew Gabbasov
2b8a9692f9 mmc: dw_mmc: Use active DDR mode flag
The card_caps bit should denote the card capability to use DDR mode,
but we need the flag indicating that the DDR mode is active.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-12 21:09:01 +02:00
Andrew Gabbasov
5af8f45cd0 mmc: Fix block length for DDR mode
Block length for write and read commands is fixed to 512 bytes
when the card is in Dual Data Rate mode. If block length read from CSD
is different, make sure the driver will use correct length
in all further calculations and settings.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-12 21:08:38 +02:00
Andrew Gabbasov
201d5ac438 mmc: Fix Dual Data Rate capability recognition
Since the driver doesn't work in 1.2V or 1.8V signaling level modes,
Dual Data Rate mode can be supported by the driver only if it is supported
by the card in regular 3.3V mode. So, check for a particular single
bit in card type field.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-12 21:08:21 +02:00
Andrew Gabbasov
786e8f818c mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.

Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.

This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.

Also, some clean up is made with errors handling and code syntax layout.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-12 21:08:06 +02:00
Jaehoon Chung
dfcb683a31 mmc: exynos_dw-mmc: change debug message
To debug more exactly, add the index for device.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2014-12-12 20:35:30 +02:00
Markus Niebel
edab723b47 MMC: add MMC_VERSION_5_0
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2014-12-12 20:34:20 +02:00
Markus Niebel
d7b2912991 MMC: fix user capacity for partitioned eMMC card
if the card claims to be high capacity and the card
is partitioned the capacity shall still be read from
ext_csd SEC_COUNT even if the resulting capacity is
smaller than 2 GiB

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2014-12-12 20:28:04 +02:00
Lubomir Popov
e75eaf100b mmc: Cosmetic fix for nicer, aligned device list printout
If print_mmc_devices() was called with a '\n' separator (as done
for example by the "mmc list" command), it offset the 2-nd and
all subsequent lines by one space. Fixing this.

Signed-off-by: Lubomir Popov <l-popov@ti.com>
2014-12-12 20:08:47 +02:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Simon Glass
964d153c0e dm: device: Add newline to debug() messages
Some of these are missing a newline. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Simon Glass
20142019a9 dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
d19de0d314 dm: i2c: Add a sandbox I2C driver
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c70c71d833 dm: i2c: Add I2C emulation driver for sandbox
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c6202d857e dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:

- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions

Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:42 -07:00
Simon Glass
59c73d7555 dm: serial_pl01x: Add missing private data size
The private data size is missing from the driver, so we store it at 0,
which causes problems when something overwrites memory at 0.

Fix this.

Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-11 13:18:41 -07:00
Masahiro Yamada
80d9ef8d40 lib: string: move strlcpy() to a common place
Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:41 -07:00
Jaiprakash Singh
1d421cc677 driver/mtd: Fix IFC compilation warnings
'eccstat' array elements might be used uninitialized

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:32 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00
Nikhil Badola
da5ce448c7 drivers: usb: fsl: Check USB Erratum A007792 applicability
Check USB Erratum A007792 applicability. If applicable, add
corresponding  property in the device tree via device tree fixup

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:11 -08:00
Nikhil Badola
ecfc19f31f drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:03 -08:00
Nikhil Badola
a1c04e2785 drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:50 -08:00
Alison Wang
8ab967b6c6 arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:24 -08:00
Minghuan Lian
da419027af arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:56 -08:00
Tom Rini
9b416a9f4c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-10 09:07:25 -05:00
Tom Rini
272a1acf1e Merge git://git.denx.de/u-boot-mpc85xx 2014-12-08 16:35:07 -05:00
Tom Rini
98d2d5e8c4 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-12-08 16:35:06 -05:00
Tom Rini
8bd60ccf53 Merge git://git.denx.de/u-boot-i2c 2014-12-08 16:35:05 -05:00
Tom Rini
1a9c8f12f2 Merge branch 'master' of git://git.denx.de/u-boot-sh 2014-12-08 09:36:26 -05:00
Masahiro Yamada
8b923a56dc blackfin: include <linux/compiler.h> rather than define __iomem
The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
2014-12-08 09:35:46 -05:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Vikas Manocha
eb8a4fe0dc serial: pl01x: avoid pl01x type check two times
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:45 -05:00
Vikas Manocha
f7e517b4eb serial: pl01x: disable as per type of pl01x
pl010 & pl011 have different control register offsets, setting it as per
the pl01x type.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
d2ca9fd2cd serial: pl01x: move all line control at same place
Receive line control uses same setting as transmit line control, also one lcrh
write is effective for both baud rate & receive line control internal update.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
2df810717e serial: pl01x: fix pl011 baud rate configuration
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
a7deea691c serial: pl01x: pass pl01x_type to set baudrate
Although we were checking the pl01x type, seems like PL010 type was being
passed by mistake.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Mark Tomlinson
f4ed36964a i2c: Correct spelling error
"diconnect" and "disconnet" should both be "disconnect".

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:22 +01:00
Mark Tomlinson
2fe50ef403 i2c: Fix deselection of muxes
Due to an uninitialised variable, when muxes were deselected, any value
could be written to the mux control register. On the PCA9548, this could
result in multiple channels being selected, thus enabling multiple
pull-up resistors, and much bus capacitance.

The fix is simply to initialise the written value to zero.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:06 +01:00
Stefan Roese
a72f80208d spi: designware_spi: Some fixes / changes
As suggested by Pavel, here some fixes to the designware SPI driver:

- Spelling fixes
- Comment for timeout added
- Removed n_bytes completely (bits_per_word is enough for this)
- Unput clock now not defined via macro. The function to
  get the clock value is now called directly from within the driver

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
5bef6fd79f spi: Add designware master SPI DM driver used on SoCFPGA
This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.

This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
10e8bf88c0 spi: Add Cadence QSPI DM driver used by SoCFPGA
This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
cc19c25e27 net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
789b3447c0 driver/ddr/fsl: Add workaround for faulty SPD
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Suresh Gupta
e2544e7a54 B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
89b94d851d powerpc/b4860qds: add xfi support
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shengzhou Liu
9b18e5199e net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
York Sun
84baed2a2b driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots
Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Joakim Tjernlund
bcb60cb9c4 Freescale t104x: Do not exclude SGMII
fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses
RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE.
This excludes testing for SGMII further down.

Remove the unconditional "else return PHY_INTERFACE_MODE_NONE"
so SGMII can be tested too.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:07 -08:00
Gregoire Gentil
956a8bae53 ns16550.c: Fix for ns16550 driver hanging on OMAP4
The same problem that is seen on some OMAP3 is also seen on some OMAP4
so include them in the test in order to prevent some hangs during SPL.

[trini: Re-word commit message, make apply cleanly]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-04 21:28:32 -05:00
Stefan Roese
fb384c4720 mtd: nand: omap_gpmc: Always use ready/busy pin
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.

Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:

Without NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.947 seconds, 2947 ticks

With NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.795 seconds, 2795 ticks

So an increase of approx. 5%.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
2014-12-04 21:28:31 -05:00
Paul Kocialkowski
aac5450ea9 omap_hsmmc: Board-specific TWL4030 MMC power initializations
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific functions,
that may still call twl4030_power_mmc_init for the default behavior.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Fix omap3_evm warning, add twl4030.h]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-04 21:28:15 -05:00
Nobuhiro Iwamatsu
9675f61077 mmc: sh_mmcif: Add support rmobile
Renesas R-Mobile/R-Car ARM SoC of MMC has the same IP that are supported by
sh_mmcif. This adds support R-Mobile/R-Car ARM SoC with the setting of the
clock support.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:16:22 +09:00
Nobuhiro Iwamatsu
7a7eb983a4 mmc: sh_mmcif: Change maximum and minimum value of MMC clock
Maximum value and the minimum value of clock for sh_mmcif instead by
base of MMC clock. This removes fixed clock, make the changes to be calculated
according to environment.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:15:52 +09:00
Nobuhiro Iwamatsu
21ea350385 mmc: sh_mmcif: Use DIV_ROUND_UP and fls instead of calculation loop
Use DIV_ROUND_UP and fls to simplify the code.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:15:11 +09:00
Paul Kocialkowski
f3e85e4825 twl4030: device-index-specific MMC power initializations, common ramp-up delay
Not every device has multiple MMC slots available, so it makes sense to enable
only the required LDOs for the available slots. Generic code in omap_hsmmc will
enable both VMMC1 and VMMC2, in doubt.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:40 -05:00
Paul Kocialkowski
95de9ab201 mmc: Board-specific MMC power initializations
Some devices may use non-standard combinations of regulators to power MMC:
this allows these devices to provide a board-specific MMC power init function
to set everything up in their own way.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:40 -05:00
Felipe Balbi
d11ac4b56d arm: omap: add support for am57xx devices
just add a few ifdefs around because this
device is very similar to dra7xxx.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
7a294c5c0a usb: phy: omap_usb_phy: fix build breakage
there's no such function usb3_phy_power(),
it's likely that author meant to call,
usb_phy_power() instead, but that's already
called properly from xhci-omap.c.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Tom Rini
88342103cc Merge git://git.denx.de/u-boot-fdt 2014-12-01 15:24:26 -05:00
Tom Rini
f4e7e2d121 Merge git://git.denx.de/u-boot-x86 2014-12-01 15:24:07 -05:00
Soeren Moch
dd1c8f1b5f sata: fix reset_sata for dwc_ahsata
- fix crash when sata device is not initialized
- remove disable_sata_clock() since it is not clear which clock for which
  device should be disabled here
- call disable_sata_clock() for mx6 in preboot_os instead

Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-12-01 10:20:19 +01:00
Fabio Estevam
a847fff11c mxc_ocotp: Do not disable the OCOTP clock after every access
Leave the OCOTP turned on, so that we subsequent access do not fail.

After enabling the thermal driver on a mx6sxsabresd board:

U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
CPU:   Temperature 48 C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
  00:01.0     - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller
In:    serial
Out:   serial
Err:   serial
Net:
(hang)

As the thermal driver accesses the ocotp registers, its clock will be disabled
afterwards.

Then when the MAC address is read (also from ocotp registers) it will cause a
hang.

Do not disable the ocotp clock to prevent this problem.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2014-12-01 10:20:19 +01:00
Fabio Estevam
7267c925b3 thermal: imx_thermal: Do not display calibration data
Printing the calibration data on every boot does not provide really useful
information:

U-Boot 2015.01-rc1-18266-ge7eb277 (Nov 24 2014 - 11:29:51)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
CPU:   Thermal calibration data: 0x5d85067d
CPU:   Temperature 33 C
Reset cause: POR
Board: MX6-SabreSD

Do not display the calibration data in order to have a cleaner boot log.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:20:18 +01:00
Hector Palacios
3d99fcbc15 mxs_ocotp: clear the error flag before initiating write operation
A previous operation may have set the error flag, which must be cleared
before a new write operation can be issued.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:42 +01:00
Hector Palacios
ad5dd7ae4b mxs_ocotp: check for errors from the OTP controller after writing
The write operation may fail when trying to write to a locked area. In
this case the ERROR bit is set in the CTRL register. Check for that
condition and return an error.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:19:41 +01:00
Hector Palacios
d8d160e420 mxs_ocotp: prevent error path from returning success
The code may goto 'fail' upon error with 'ret' variable set to an error
code, but this variable was being overwritten by a final preparation
function to restore the HCLK, so success was (in general) returned even
after an error was hit previously.

With this change, the function may now return success even if the final
preparation function fails, but it's probably enough to print a message
because (if successful) the real programming of the fuses has already
completed.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:41 +01:00
Tom Rini
e17e998d7f Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2014-11-27 13:10:04 -05:00
Masahiro Yamada
149c751dc7 usb: UniPhier: support OF configuration
If CONFIG_OF_CONTROL is defined, search device tree nodes that are
compatible with "panasonic,uniphier-ehci" and take the base address
from their "reg" property.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
625177d27e serial: UniPhier: support OF configuration
This commit implements the ofdata_to_platdata handler for the UniPhier
serial driver and adds serial device nodes to the device tree sources.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
0bd4e39d2b fdt: remove fdtdec_get_alias_node() function
The fdt_path_offset() checks an alias too.

fdtdec_get_alias_node(blob, "foo") is equivalent to
fdt_path_offset(blob, "foo").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-27 09:12:30 -07:00
Marek Vasut
b19157bf3f mtd: nand: s3c: Unify the register definition and naming
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
2014-11-26 23:21:43 -06:00
Sanchayan Maity
2260457341 mtd/nand/vf610_nfc: Disable subpage writes
This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.

Patch has been tested on a Colibri VF61 module.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2014-11-26 19:53:49 -06:00
Masahiro Yamada
f09eb52b3f mtd: denali: set some registers after nand_scan_ident()
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc.  Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices.  The device parameters detected
during nand_scan_ident() are more trustworthy.

This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
2014-11-26 19:53:22 -06:00
Masahiro Yamada
65e4145a20 mtd: denali: use CONFIG_SYS_NAND_SELF_INIT
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().

CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail().  It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux.  Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
2014-11-26 19:53:19 -06:00
Rostislav Lisovy
35c204d8a9 nand: reinstate lazy bad block scanning
Commit ff94bc40af
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3
("NAND: Scan bad blocks lazily.").

Reinstate the change as by commit
fb49454b1b
("nand: reinstate lazy bad block scanning")

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
2014-11-26 19:51:51 -06:00
Tom Rini
85bafb6da4 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-11-26 11:23:26 -05:00
Tom Rini
21008ad638 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26 11:22:29 -05:00
Tom Rini
878cd63e02 Merge branch 'master' of http://git.denx.de/u-boot-samsung 2014-11-26 11:21:16 -05:00
Simon Glass
8c6ec412b4 bios_emulator: Always print errors when opcode decode fails
This is a rare event and should not happen. When it does it is confusing to
work out why. At least we should print a message.

Adjust the emulator to always print decode errors to the console.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
b3521f2e49 bios_emulator: Add an option to enable debugging
At present there are DEBUG options spread around the place. If you enable
one and not another you can end up with an emulator that does not work,
since each file can have a different view of what the registers look like.
To fix this, create a global CONFIG_X86EMU_DEBUG option that keeps
everything consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
a3c700ec76 bios_emulator: Allow a custom interrupt handler to be installed
Sometime we want to provide an interrupt handler for the ROM, Add a
function to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
4c59f95327 bios_emulator: Add vesa support and allow ROMs to be passed in as data
As well as locating the ROM on the PCI bus, allow the ROM to be supplied to
the emulator. Split the init up a little so that callers can supply their
own interrupt routines. Also allow a vesa mode to be provided, to be
selected once the BIOS run is complete.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
ad6edca379 bios_emulator: Allow x86 to use the emulator
There is an implicit assumption that x86 machines want to use raw I/O in the
BIOS emulator, but this should be selectable. Add an CONFIG_X86EMU_RAW_IO
option to control it instead.

Also fix a few bugs which cause warnings on x86 and adjust the Makefile to
remove the assumption that only PowerPC uses the emulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
998110241b x86: video: Add video driver for bare x86 boards
Add a very simple driver which uses vesa to discover the video mode and
then provides a frame buffer for use by U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-11-25 07:11:16 -07:00
Simon Glass
6854f87cbc pci: Add general support for execution of video ROMs
Some platforms don't have native code for dealing with their video
hardware. In some cases they use a binary blob to set it up and perform
required actions like setting the video mode. This approach is a hangover
from the old PC days where a ROM was provided and executed during startup.

Even now, these ROMs are supplied as a way to set up video. It avoids the
code for every video chip needing to be provided in the boot loader. But
it makes the video much less flexible - e.g. it is not possible to do
anything else while the video init is happening (including waiting hundreds
of milliseconds for display panels to start up).

In any case, to deal with this sad state of affairs, provide an API for
execution of x86 video ROMs, either natively or through emulation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:14 -07:00
Simon Glass
176bf4ce0c Introduce a header file for the BIOS emulator
We should have a public header so that users can avoid defining functions
themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
e8a552eb62 pci: Add functions to read and write a BAR address
Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
c6577f7219 rtc: mc146818: Set up RTC at start of day
Provide a function to set up the RTC ready for use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Luc Verhaegen
2d7a084ba0 sunxi: video: Add simplefb support
Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as
 disussed on the devicetree list]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>.
2014-11-25 13:38:46 +01:00
Hans de Goede
211717a463 sunxi: video: Add sun6i support
Besided needing the usual sun6i specific ahb1_reset bits poking, it turns out
that sun6i also needs the drc to be taken out of reset and clocked even though
it is in pass-through mode.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-11-25 13:38:46 +01:00
Luc Verhaegen
7f2c521f90 sunxi: video: Add cfb console driver for sunxi
This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.

This code is enabled when HPD detects an attached monitor.

Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.

cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Nikhil Badola
f3dff695e1 drivers : usb: fsl: Implement usb Erratum A007798 workaround
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:04 -08:00