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https://github.com/brain-hackers/u-boot-brain
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5f7f70c171
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
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| .. | ||
| bios_emulator | ||
| block | ||
| bootcount | ||
| core | ||
| crypto | ||
| ddr/fsl | ||
| demo | ||
| dfu | ||
| dma | ||
| fpga | ||
| gpio | ||
| hwmon | ||
| i2c | ||
| input | ||
| memory | ||
| misc | ||
| mmc | ||
| mtd | ||
| net | ||
| pci | ||
| pcmcia | ||
| power | ||
| pwm | ||
| qe | ||
| rtc | ||
| serial | ||
| soc | ||
| sound | ||
| spi | ||
| thermal | ||
| tpm | ||
| twserial | ||
| usb | ||
| video | ||
| watchdog | ||
| Kconfig | ||
| Makefile | ||