Commit Graph

338 Commits

Author SHA1 Message Date
Haiying Wang
4e190b03aa Make Freescale local bus registers available for both 83xx and 85xx.
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-29 11:12:53 -05:00
Peter Tyser
4442f45b0e 85xx: Update MPC85xx_PORDEVSR_IO_SEL mask
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
processors have a 3-bit wide IO_SEL field but have the most
significant bit is wired to 0 so this change should not affect
them.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-27 16:45:43 -05:00
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Anton Vorontsov
6f9cc6608b mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:01 -05:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Timur Tabi
681c02d05b 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG
Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot
to add a comment that the correct value disagrees with the 8544 reference
manual.  The changelog for that commit is also wrong, as it says "bit 28"
when it should be "bit 24".

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-10-21 11:15:20 +02:00
Wolfgang Denk
f82642e338 Merge 'next' branch
Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18 21:59:44 +02:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Haiying Wang
dbbbb3abef Make DDR interleaving mode work correctly
Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Kumar Gala
54e091d3b6 85xx: Export invalidate_{i,d}cache and add flush_dcache
Added the ability for C code to invalidate the i/d-cache's and
to flush the d-cache.  This allows us to more efficient change mappings
from cache-able to cache-inhibited.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-18 21:54:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
richardretanubun
c68a05feeb Adds two more ethernet interface to 83xx
Added as a convenience for other platforms that uses MPC8360 (has 8 UCC).
Six eth interface is chosen because the platform I am using combines
UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth.

Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-10-18 21:54:00 +02:00
Yuri Tikhonov
bf29e0ea0a ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-17 13:02:42 +02:00
Kumar Gala
f7d190b1c0 85xx: Using proper I2C source clock divider for MPC8544
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
bit 26, instead it should be bit 28.  This caused in incorrect
interpretation of the i2c_clk which is the same as the SEC clk on
MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
in PORDEVSR2.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-17 10:51:35 +02:00
Jason Jin
c0391111c3 Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-07 15:37:08 -05:00
Stefan Roese
5ff889349d ppc4xx: Move ppc4xx specific prototypes to ppc4xx header
This patch moves some 4xx specific prototypes out of include common.h
to a ppc4xx specific header.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 14:11:12 +02:00
Stefan Roese
c351575c22 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-09-08 10:35:49 +02:00
Mark Jackson
f5c3ba7978 Allow console input to be disabled
Added new CONFIG_DISABLE_CONSOLE define and GD_FLG_DISABLE_CONSOLE.

When CONFIG_DISABLE_CONSOLE is defined, setting
GD_FLG_DISABLE_CONSOLE disables all console input and output.

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
2008-09-06 22:36:54 +02:00
Adam Graham
f6b6c45840 ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:04:16 +02:00
Nick Spence
46497056ae mpc83xx: Store and display Arbiter Event Register values
Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-03 16:06:57 -05:00
Kumar Gala
ef50d6c06e mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27 11:43:54 -05:00
Kumar Gala
6fb1b73468 FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when
setting up DDR.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00
Kumar Gala
58e5e9aff1 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers.  (83xx, 85xx, 86xx).

The code is broken up into the following steps:
	GET_SPD
	COMPUTE_DIMM_PARMS
	COMPUTE_COMMON_PARMS
	GATHER_OPTS
	ASSIGN_ADDRESSES
	COMPUTE_REGS
	PROGRAM_REGS

This allows us to share more code an easily allow for board specific code
overrides.

Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 02:05:58 +02:00
Kumar Gala
f784e32b4b FSL DDR: Provide a generic set_ddr_laws()
Provide a helper function that will setup the last available
LAWs (upto 2) for DDR.  Useful for SPD/dyanmic DDR setting code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 02:05:55 +02:00
Nick Spence
002d27caf2 MPC83XX: Add miscellaneous registers and #defines to support MPC83xx family devices
This patch adds elements to the 83xx sysconf structure and #define values that are used
by mpc83xx family devices.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-25 17:04:40 -05:00
Prodyut Hazarika
079589bcfb ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 10:31:16 +02:00
Stefan Roese
f2302d4430 Fix merge problems
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-06 14:05:38 +02:00
Stefan Roese
60204d06ed ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-18 12:31:25 +02:00
Ricardo Ribalda Delgado
d865fd0980 ppc4xx: CPU PPC440x5 on Virtex5 FX
-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
2008-07-18 12:30:50 +02:00
Stefan Roese
42246dacf6 Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next 2008-07-17 10:41:06 +02:00
Kumar Gala
7f9f4347cf 85xx: Add some L1/L2 SPR register definitions
Add new L1/L2 SPRs related to e500mc cache config and control.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:19:59 -05:00
Kim Phillips
6b70ffb9d1 fdt: add crypto node handling for MPC8{3, 5}xxE processors
Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 17:01:29 -05:00
Stefan Roese
3a82113ed5 ppc4xx: Add 460SX UIC defines
Only the really needed ones are added (cascading and EMAC/MAL).

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
5de851403b ppc4xx: Rework 440GX UIC handling
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.

Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
d1631fe1a0 ppc4xx: Consolidate PPC4xx UIC defines
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
4fb25a3db3 ppc4xx: Consolidate PPC4xx UIC defines
This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Stefan Roese
7ee2619c20 ppc4xx: Consolidate PPC4xx EBC defines
This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
2e2050842e ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller
This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
ad7382d828 ppc4xx: Add AMCC/IBM DDR2 SDRAM ECC Field Mnemonics
Add additional DDR2 SDRAM memory controller DCR mneomnics, condition
revision ID DCR based on 405EX, and add field mnemonics for bus error
status and ECC error status registers.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
5b457d0073 PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.

Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:12 +02:00
Feng Kan
96e5fc0e6a ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:12 +02:00
Jon Loeliger
859f24350e Merge commit 'wd/master' 2008-07-10 12:05:32 -05:00
Stefan Roese
5d812b8b4a ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.

Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-10 09:14:01 +02:00
Jason Jin
3473ab7372 Feed the watchdog in u-boot for 8610 board.
The watchdog on 8610 board is enabled by setting sw[6]
to on. Once enabled, the watchdog can not be disabled
by software. So feed the dog in u-boot is necessary for
normal operation.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-07-07 11:29:48 -05:00
Wolfgang Denk
3070a9a3cb Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx 2008-07-07 00:32:47 +02:00
Kumar Gala
4928e97c85 PPC: Added fls, fls64, __ilog2_u64, and ffs64 to bitops
fls64, __ilog2_u64, ffs64 are variants that work on an u64,
and fls is used to implement them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-01 21:47:12 +02:00
Kim Phillips
4890246a2c mpc83xx: move CPU_TYPE_ENTRY over to processor.h
to avoid this:

cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined
In file included from cpu.c:33:
/home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-25 16:34:29 -05:00
Anatolij Gustschin
96026d42fa Fix 4xx build issue
Building for 4xx doesn't work since commit 4dbdb768:

In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1

This patch fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:48:45 +02:00
Becky Bruce
b57ca3e128 Change bd/gd memsize/ram_size to be phys_size_t.
Currently, both are defined as an unsigned long, but
should be phys_size_t. This should result in no real change,
since phys_size_t is currently an unsigned long for all the
default configs.  Also add print_lnum to cmd_bdinfo to deal
with the potentially wider memsize.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 00:54:53 +02:00