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PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

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While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.

Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Grant Erickson 2008-07-09 11:55:46 -07:00 committed by Stefan Roese
parent 0ce5c8675b
commit 5b457d0073
1 changed files with 4 additions and 0 deletions
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4
include/asm-ppc/ppc4xx-sdram.h
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@ -354,7 +354,11 @@
/*
* Memory controller registers
*/
#ifndef CONFIG_405EX
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#else
#define SDRAM_MCSTAT 0x1F /* memory controller status */
#endif
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */