brain-hackers_pepepper-mirror/u-boot-brain
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

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This commit is contained in:
Stefan Roese 2008-09-08 10:35:49 +02:00
commit c351575c22
69 changed files with 772 additions and 389 deletions
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2
board/apollon/config.mk
View File

@ -13,7 +13,7 @@
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
TEXT_BASE = 0x80e80000
TEXT_BASE = 0x83e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.

4
board/bmw/m48t59y.c
View File

@ -299,8 +299,7 @@ rtc_get( struct rtc_time *tmp )
return 0;
}
void
rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
m48_tod_set(tmp->tm_year, /* 1980-2079 */
tmp->tm_mon, /* 01-12 */
@ -315,6 +314,7 @@ rtc_set( struct rtc_time *tmp )
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
void

4
board/cray/L1/L1.c
View File

@ -181,9 +181,9 @@ int rtc_get (struct rtc_time *tmp)
{
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
return;
return 0;
}
void rtc_reset (void)
{

4
board/etin/debris/phantom.c
View File

@ -254,7 +254,7 @@ int rtc_get( struct rtc_time *tmp)
return 0;
}
void rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
if (phantom_flag < 0)
phantom_flag = get_phantom_flag();
@ -307,6 +307,8 @@ void rtc_set( struct rtc_time *tmp )
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
}
return 0;
}
#endif

4
board/mousse/m48t59y.c
View File

@ -299,8 +299,7 @@ rtc_get( struct rtc_time *tmp )
return 0;
}
void
rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
m48_tod_set(tmp->tm_year, /* 1980-2079 */
tmp->tm_mon, /* 01-12 */
@ -315,6 +314,7 @@ rtc_set( struct rtc_time *tmp )
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
void

2
board/tqc/tqm8272/Makefile
View File

@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

276
board/tqc/tqm8272/nand.c Normal file
View File

@ -0,0 +1,276 @@
/*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "tqm8272.h"
/* UPM pattern for bus clock = 66.7 MHz */
static const uint upmTable67[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
/* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 100 MHz */
static const uint upmTable100[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
/* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 133.3 MHz */
static const uint upmTable133[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
/* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
static int chipsel = 0;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
static u8 hwctl = 0;
static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
if (hwctl & 0x1) {
WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
} else if (hwctl & 0x2) {
WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
} else {
WRITE_NAND(byte, base);
}
}
static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
}
if (cmd != NAND_CMD_NONE)
upmnand_write_byte (mtd, cmd);
}
static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
return READ_NAND(base);
}
static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
{
/* constant delay (see also tR in the datasheet) */
udelay(12); \
return 1;
}
#ifndef CONFIG_NAND_SPL
static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i< len; i++)
buf[i] = *base;
}
static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i< len; i++)
*base = buf[i];
}
static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i < len; i++)
if (buf[i] != *base)
return -1;
return 0;
}
#endif /* #ifndef CONFIG_NAND_SPL */
void board_nand_select_device(struct nand_chip *nand, int chip)
{
chipsel = chip;
}
int board_nand_init(struct nand_chip *nand)
{
static int UpmInit = 0;
volatile immap_t * immr = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immr->im_memctl;
if (hwinf.nand == 0) return -1;
/* Setup the UPM */
if (UpmInit == 0) {
switch (hwinf.busclk_real) {
case 100000000:
upmconfig (UPMB, (uint *) upmTable100,
sizeof (upmTable100) / sizeof (uint));
break;
case 133333333:
upmconfig (UPMB, (uint *) upmTable133,
sizeof (upmTable133) / sizeof (uint));
break;
default:
upmconfig (UPMB, (uint *) upmTable67,
sizeof (upmTable67) / sizeof (uint));
break;
}
UpmInit = 1;
}
/* Setup the memctrl */
memctl->memc_or3 = CFG_NAND_OR;
memctl->memc_br3 = CFG_NAND_BR;
memctl->memc_mbmr = (MxMR_OP_NORM);
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = upmnand_hwcontrol;
nand->read_byte = upmnand_read_byte;
nand->dev_ready = tqm8272_dev_ready;
#ifndef CONFIG_NAND_SPL
nand->write_buf = tqm8272_write_buf;
nand->read_buf = tqm8272_read_buf;
nand->verify_buf = tqm8272_verify_buf;
#endif
/*
* Select required NAND chip
*/
board_nand_select_device(nand, 0);
return 0;
}
#endif

279
board/tqc/tqm8272/tqm8272.c
View File

@ -31,6 +31,7 @@
#include <pci.h>
#include <asm/m8260_pci.h>
#endif
#include "tqm8272.h"
#if 0
#define deb_printf(fmt,arg...) \
@ -208,112 +209,6 @@ const iop_conf_t iop_conf_tab[4][32] = {
}
};
#define _NOT_USED_ 0xFFFFFFFF
/* UPM pattern for bus clock = 66.7 MHz */
static const uint upmTable67[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
/* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 100 MHz */
static const uint upmTable100[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
/* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 133.3 MHz */
static const uint upmTable133[] =
{
/* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> unused */
/* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
/* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
/* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
static int chipsel = 0;
/* UPM pattern for slow init */
static const uint upmTableSlow[] =
{
@ -616,31 +511,6 @@ static inline int scanChar (char *p, int len, unsigned long *number)
return akt;
}
typedef struct{
int Bus;
int flash;
int flash_nr;
int ram;
int ram_cs;
int nand;
int nand_cs;
int eeprom;
int can;
unsigned long cpunr;
unsigned long option;
int SecEng;
int cpucl;
int cpmcl;
int buscl;
int busclk_real_ok;
int busclk_real;
unsigned char OK;
unsigned char ethaddr[20];
} HWIB_INFO;
HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
0, 0, 0, 0, 0, 0};
static int dump_hwib(void)
{
HWIB_INFO *hw = &hwinf;
@ -1062,153 +932,6 @@ int update_flash_size (int flash_size)
}
#endif
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
static u8 hwctl = 0;
static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
if (hwctl & 0x1) {
WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
} else if (hwctl & 0x2) {
WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
} else {
WRITE_NAND(byte, base);
}
}
static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
return READ_NAND(base);
}
static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
{
/* constant delay (see also tR in the datasheet) */
udelay(12); \
return 1;
}
#ifndef CONFIG_NAND_SPL
static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i< len; i++)
buf[i] = *base;
}
static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i< len; i++)
*base = buf[i];
}
static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
int i;
for (i = 0; i < len; i++)
if (buf[i] != *base)
return -1;
return 0;
}
#endif /* #ifndef CONFIG_NAND_SPL */
void board_nand_select_device(struct nand_chip *nand, int chip)
{
chipsel = chip;
}
int board_nand_init(struct nand_chip *nand)
{
static int UpmInit = 0;
volatile immap_t * immr = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immr->im_memctl;
if (hwinf.nand == 0) return -1;
/* Setup the UPM */
if (UpmInit == 0) {
switch (hwinf.busclk_real) {
case 100000000:
upmconfig (UPMB, (uint *) upmTable100,
sizeof (upmTable100) / sizeof (uint));
break;
case 133333333:
upmconfig (UPMB, (uint *) upmTable133,
sizeof (upmTable133) / sizeof (uint));
break;
default:
upmconfig (UPMB, (uint *) upmTable67,
sizeof (upmTable67) / sizeof (uint));
break;
}
UpmInit = 1;
}
/* Setup the memctrl */
memctl->memc_or3 = CFG_NAND_OR;
memctl->memc_br3 = CFG_NAND_BR;
memctl->memc_mbmr = (MxMR_OP_NORM);
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = upmnand_hwcontrol;
nand->read_byte = upmnand_read_byte;
nand->write_byte = upmnand_write_byte;
nand->dev_ready = tqm8272_dev_ready;
#ifndef CONFIG_NAND_SPL
nand->write_buf = tqm8272_write_buf;
nand->read_buf = tqm8272_read_buf;
nand->verify_buf = tqm8272_verify_buf;
#endif
/*
* Select required NAND chip
*/
board_nand_select_device(nand, 0);
return 0;
}
#endif
#ifdef CONFIG_PCI
struct pci_controller hose;

53
board/tqc/tqm8272/tqm8272.h Normal file
View File

@ -0,0 +1,53 @@
/*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TQM8272_HEADER_H
#define _TQM8272_HEADER_H
#define _NOT_USED_ 0xFFFFFFFF
typedef struct{
int Bus;
int flash;
int flash_nr;
int ram;
int ram_cs;
int nand;
int nand_cs;
int eeprom;
int can;
unsigned long cpunr;
unsigned long option;
int SecEng;
int cpucl;
int cpmcl;
int buscl;
int busclk_real_ok;
int busclk_real;
unsigned char OK;
unsigned char ethaddr[20];
} HWIB_INFO;
static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
0, 0, 0, 0, 0, 0};
#endif

5
common/cmd_bootm.c
View File

@ -246,7 +246,7 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ret = boot_get_ramdisk (argc, argv, &images, IH_INITRD_ARCH,
&images.rd_start, &images.rd_end);
if (ret) {
puts ("Ramdisk image is corrupt\n");
puts ("Ramdisk image is corrupt or invalid\n");
return 1;
}
@ -361,7 +361,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong load_end = 0;
int ret;
bootm_start(cmdtp, flag, argc, argv);
if (bootm_start(cmdtp, flag, argc, argv))
return 1;
/*
* We have reached the point of no return: we are going to

28
common/cmd_date.c
View File

@ -56,18 +56,30 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
rtc_reset ();
} else {
/* initialize tm with current time */
rtc_get (&tm);
/* insert new date & time */
if (mk_date (argv[1], &tm) != 0) {
puts ("## Bad date format\n");
break;
rcode = rtc_get (&tm);
if(!rcode) {
/* insert new date & time */
if (mk_date (argv[1], &tm) != 0) {
puts ("## Bad date format\n");
break;
}
/* and write to RTC */
rcode = rtc_set (&tm);
if(rcode)
puts("## Set date failled\n");
} else {
puts("## Get date failled\n");
}
/* and write to RTC */
rtc_set (&tm);
}
/* FALL TROUGH */
case 1: /* get date & time */
rtc_get (&tm);
rcode = rtc_get (&tm);
if (rcode) {
puts("## Get date failled\n");
break;
}
printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,

69
common/cmd_jffs2.c
View File

@ -51,7 +51,7 @@
* mtdids=<idmap>[,<idmap>,...]
*
* <idmap> := <dev-id>=<mtd-id>
* <dev-id> := 'nand'|'nor'<dev-num>
* <dev-id> := 'nand'|'nor'|'onenand'<dev-num>
* <dev-num> := mtd device number, 0...
* <mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)
*
@ -103,6 +103,13 @@
#include <nand.h>
#endif /* !CONFIG_NAND_LEGACY */
#endif
#if defined(CONFIG_CMD_ONENAND)
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <onenand_uboot.h>
#endif
/* enable/disable debugging messages */
#define DEBUG_JFFS
#undef DEBUG_JFFS
@ -400,6 +407,43 @@ static int part_validate_nand(struct mtdids *id, struct part_info *part)
#endif
}
/**
* Performs sanity check for supplied OneNAND flash partition.
* Table of existing OneNAND flash devices is searched and partition device
* is located. Alignment with the granularity of nand erasesize is verified.
*
* @param id of the parent device
* @param part partition to validate
* @return 0 if partition is valid, 1 otherwise
*/
static int part_validate_onenand(struct mtdids *id, struct part_info *part)
{
#if defined(CONFIG_CMD_ONENAND)
/* info for OneNAND chips */
struct mtd_info *mtd;
mtd = &onenand_mtd;
if ((unsigned long)(part->offset) % mtd->erasesize) {
printf("%s%d: partition (%s) start offset"
"alignment incorrect\n",
MTD_DEV_TYPE(id->type), id->num, part->name);
return 1;
}
if (part->size % mtd->erasesize) {
printf("%s%d: partition (%s) size alignment incorrect\n",
MTD_DEV_TYPE(id->type), id->num, part->name);
return 1;
}
return 0;
#else
return 1;
#endif
}
/**
* Performs sanity check for supplied partition. Offset and size are verified
* to be within valid range. Partition type is checked and either
@ -436,6 +480,8 @@ static int part_validate(struct mtdids *id, struct part_info *part)
return part_validate_nand(id, part);
else if (id->type == MTD_DEV_TYPE_NOR)
return part_validate_nor(id, part);
else if (id->type == MTD_DEV_TYPE_ONENAND)
return part_validate_onenand(id, part);
else
DEBUGF("part_validate: invalid dev type\n");
@ -755,7 +801,15 @@ static int device_validate(u8 type, u8 num, u32 *size)
#else
printf("support for NAND devices not present\n");
#endif
}
} else if (type == MTD_DEV_TYPE_ONENAND) {
#if defined(CONFIG_CMD_ONENAND)
*size = onenand_mtd.size;
return 0;
#else
printf("support for OneNAND devices not present\n");
#endif
} else
printf("Unknown defice type %d\n", type);
return 1;
}
@ -1065,8 +1119,8 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_
#endif /* #ifdef CONFIG_JFFS2_CMDLINE */
/**
* Parse device id string <dev-id> := 'nand'|'nor'<dev-num>, return device
* type and number.
* Parse device id string <dev-id> := 'nand'|'nor'|'onenand'<dev-num>,
* return device type and number.
*
* @param id string describing device id
* @param ret_id output pointer to next char after parse completes (output)
@ -1085,6 +1139,9 @@ int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num)
} else if (strncmp(p, "nor", 3) == 0) {
*dev_type = MTD_DEV_TYPE_NOR;
p += 3;
} else if (strncmp(p, "onenand", 7) == 0) {
*dev_type = MTD_DEV_TYPE_ONENAND;
p += 7;
} else {
printf("incorrect device type in %s\n", id);
return 1;
@ -1489,7 +1546,7 @@ static int parse_mtdids(const char *const ids)
while(p && (*p != '\0')) {
ret = 1;
/* parse 'nor'|'nand'<dev-num> */
/* parse 'nor'|'nand'|'onenand'<dev-num> */
if (id_parse(p, &p, &type, &num) != 0)
break;
@ -2181,7 +2238,7 @@ U_BOOT_CMD(
"'mtdids' - linux kernel mtd device id <-> u-boot device id mapping\n\n"
"mtdids=<idmap>[,<idmap>,...]\n\n"
"<idmap> := <dev-id>=<mtd-id>\n"
"<dev-id> := 'nand'|'nor'<dev-num>\n"
"<dev-id> := 'nand'|'nor'|'onenand'<dev-num>\n"
"<dev-num> := mtd device number, 0...\n"
"<mtd-id> := unique device tag used by linux kernel to find mtd device (mtd->name)\n\n"
"'mtdparts' - partition list\n\n"

10
common/cmd_load.c
View File

@ -38,7 +38,7 @@ static ulong load_serial_ymodem (ulong offset);
#endif
#if defined(CONFIG_CMD_LOADS)
static ulong load_serial (ulong offset);
static ulong load_serial (long offset);
static int read_record (char *buf, ulong len);
# if defined(CONFIG_CMD_SAVES)
static int save_serial (ulong offset, ulong size);
@ -53,7 +53,7 @@ static int do_echo = 1;
#if defined(CONFIG_CMD_LOADS)
int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong offset = 0;
long offset = 0;
ulong addr;
int i;
char *env_echo;
@ -72,7 +72,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#ifdef CFG_LOADS_BAUD_CHANGE
if (argc >= 2) {
offset = simple_strtoul(argv[1], NULL, 16);
offset = simple_strtol(argv[1], NULL, 16);
}
if (argc == 3) {
load_baudrate = (int)simple_strtoul(argv[2], NULL, 10);
@ -95,7 +95,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#else /* ! CFG_LOADS_BAUD_CHANGE */
if (argc == 2) {
offset = simple_strtoul(argv[1], NULL, 16);
offset = simple_strtol(argv[1], NULL, 16);
}
#endif /* CFG_LOADS_BAUD_CHANGE */
@ -141,7 +141,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
static ulong
load_serial (ulong offset)
load_serial (long offset)
{
char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */
char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */

20
common/console.c
View File

@ -162,6 +162,11 @@ void fprintf (int file, const char *fmt, ...)
int getc (void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
return 0;
#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Get from the standard input */
return fgetc (stdin);
@ -173,6 +178,11 @@ int getc (void)
int tstc (void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
return 0;
#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Test the standard input */
return ftstc (stdin);
@ -189,6 +199,11 @@ void putc (const char c)
return;
#endif
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
return;
#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputc (stdout, c);
@ -205,6 +220,11 @@ void puts (const char *s)
return;
#endif
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
return;
#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputs (stdout, s);

5
common/image.c
View File

@ -749,7 +749,7 @@ int genimg_has_config (bootm_headers_t *images)
* rd_start and rd_end are set to ramdisk start/end addresses if
* ramdisk image is found and valid
*
* 1, if ramdisk image is found but corrupted
* 1, if ramdisk image is found but corrupted, or invalid
* rd_start and rd_end are set to 0 if no ramdisk exists
*/
int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
@ -936,6 +936,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
default:
puts ("Wrong Ramdisk Image Format\n");
rd_data = rd_len = rd_load = 0;
return 1;
}
#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO)
@ -1516,7 +1517,7 @@ int boot_get_fdt (int flag, int argc, char *argv[], bootm_headers_t *images,
}
break;
default:
fdt_error ("Did not find a cmdline Flattened Device Tree");
puts ("ERROR: Did not find a cmdline Flattened Device Tree\n");
goto error;
}

16
config.mk
View File

@ -44,22 +44,6 @@ PLATFORM_RELFLAGS =
PLATFORM_CPPFLAGS =
PLATFORM_LDFLAGS =
#
# When cross-compiling on NetBSD, we have to define __PPC__ or else we
# will pick up a va_list declaration that is incompatible with the
# actual argument lists emitted by the compiler.
#
# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3]
ifeq ($(ARCH),ppc)
ifeq ($(CROSS_COMPILE),powerpc-netbsd-)
PLATFORM_CPPFLAGS+= -D__PPC__
endif
ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
PLATFORM_CPPFLAGS+= -D__PPC__
endif
endif
ifeq ($(ARCH),arm)
ifeq ($(CROSS_COMPILE),powerpc-netbsd-)
PLATFORM_CPPFLAGS+= -D__ARM__

6
cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int wr; /* Write Recovery */
unsigned int dll_res; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
unsigned int caslat; /* CAS# latency */
unsigned int caslat = 0;/* CAS# latency */
/* BT: Burst Type (0=Sequential, 1=Interleaved) */
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
0x6, /* 2.5 clocks */
0x3 /* 3.0 clocks */
};
caslat = mode_caslat_table[cas_latency - 1];
caslat = mode_caslat_table[cas_latency - 1];
} else {
printf("Warning: unknown cas_latency %d\n", cas_latency);
}
#elif defined(CONFIG_FSL_DDR2)
caslat = cas_latency;

4
cpu/s3c44b0/cpu.c
View File

@ -188,7 +188,7 @@ int rtc_get (struct rtc_time* tm)
return 0;
}
void rtc_set (struct rtc_time* tm)
int rtc_set (struct rtc_time* tm)
{
if(tm->tm_year < 2000)
tm->tm_year -= 1900;
@ -204,6 +204,8 @@ void rtc_set (struct rtc_time* tm)
BCDMIN = HEX2BCD(tm->tm_min);
BCDSEC = HEX2BCD(tm->tm_sec);
RTCCON &= 1;
return 0;
}
void rtc_reset (void)

6
drivers/rtc/bfin_rtc.c
View File

@ -53,7 +53,7 @@ int rtc_init(void)
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
void rtc_set(struct rtc_time *tmp)
int rtc_set(struct rtc_time *tmp)
{
unsigned long remain, days, hrs, mins, secs;
@ -61,7 +61,7 @@ void rtc_set(struct rtc_time *tmp)
if (tmp == NULL) {
puts("Error setting the date/time\n");
return;
return -1;
}
wait_for_complete();
@ -82,6 +82,8 @@ void rtc_set(struct rtc_time *tmp)
/* Encode these time values into our RTC_STAT register */
bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs));
return 0;
}
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */

4
drivers/rtc/ds12887.c
View File

@ -154,7 +154,7 @@ else
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar save_ctrl_b;
uchar sec, min, hour, mday, wday, mon, year;
@ -202,6 +202,8 @@ void rtc_set (struct rtc_time *tmp)
/* enables the RTC to update the regs */
save_ctrl_b &= ~RTC_CB_SET;
rtc_write(RTC_CONTROL_B, save_ctrl_b);
return 0;
}
void rtc_reset (void)

5
drivers/rtc/ds1302.c
View File

@ -287,8 +287,7 @@ rtc_get(struct rtc_time *tmp)
return rel;
}
void
rtc_set(struct rtc_time *tmp)
int rtc_set(struct rtc_time *tmp)
{
struct ds1302_st bbclk;
unsigned char b=0;
@ -326,6 +325,8 @@ rtc_set(struct rtc_time *tmp)
write_ser_drv(0x8e,&b,1); /* disable write protect */
write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */
return 0;
}
#endif

6
drivers/rtc/ds1306.c
View File

@ -141,7 +141,7 @@ int rtc_get (struct rtc_time *tmp)
/* ------------------------------------------------------------------------- */
/* set clock time in DS1306 RTC and in MPC8xx RTC */
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@ -209,6 +209,8 @@ void rtc_set (struct rtc_time *tmp)
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
@ -371,7 +373,7 @@ int rtc_get (struct rtc_time *tmp)
/* ------------------------------------------------------------------------- */
/* set clock time from *tmp in DS1306 RTC */
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {

4
drivers/rtc/ds1307.c
View File

@ -128,7 +128,7 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@ -144,6 +144,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}

4
drivers/rtc/ds1337.c
View File

@ -132,7 +132,7 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar century;
@ -150,6 +150,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}

4
drivers/rtc/ds1374.c
View File

@ -160,7 +160,7 @@ int rtc_get (struct rtc_time *tm){
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp){
int rtc_set (struct rtc_time *tmp){
unsigned long time;
unsigned i;
@ -186,6 +186,8 @@ void rtc_set (struct rtc_time *tmp){
/* Start clock */
rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
return 0;
}
/*

4
drivers/rtc/ds1556.c
View File

@ -120,7 +120,7 @@ int rtc_get( struct rtc_time *tmp )
return 0;
}
void rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
@ -146,6 +146,8 @@ void rtc_set( struct rtc_time *tmp )
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)

4
drivers/rtc/ds164x.c
View File

@ -119,7 +119,7 @@ int rtc_get( struct rtc_time *tmp )
return 0;
}
void rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
@ -145,6 +145,8 @@ void rtc_set( struct rtc_time *tmp )
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)

4
drivers/rtc/ds174x.c
View File

@ -117,7 +117,7 @@ int rtc_get( struct rtc_time *tmp )
return 0;
}
void rtc_set( struct rtc_time *tmp )
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
@ -143,6 +143,8 @@ void rtc_set( struct rtc_time *tmp )
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)

4
drivers/rtc/ds3231.c
View File

@ -134,7 +134,7 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar century;
@ -152,6 +152,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}

4
drivers/rtc/isl1208.c
View File

@ -118,7 +118,7 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@ -139,6 +139,8 @@ void rtc_set (struct rtc_time *tmp)
/* disable write */
rtc_write(RTC_STAT_REG_ADDR,
rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
return 0;
}
void rtc_reset (void)

4
drivers/rtc/m41t11.c
View File

@ -143,7 +143,7 @@ int rtc_get (struct rtc_time *tmp)
return rel;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar data[RTC_REG_CNT];
@ -176,6 +176,8 @@ void rtc_set (struct rtc_time *tmp)
}
#endif
i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT);
return 0;
}
void rtc_reset (void)

8
drivers/rtc/m41t60.c
View File

@ -193,12 +193,12 @@ int rtc_get(struct rtc_time *tmp)
return 0;
}
void rtc_set(struct rtc_time *tmp)
int rtc_set(struct rtc_time *tmp)
{
uchar *const data = rtc_validate();
if (!data)
return;
return -1;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@ -214,8 +214,10 @@ void rtc_set(struct rtc_time *tmp)
data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07;
if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) {
printf("I2C write failed in rtc_set()\n");
return;
return -1;
}
return 0;
}
void rtc_reset(void)

8
drivers/rtc/m41t62.c
View File

@ -96,7 +96,7 @@ int rtc_get(struct rtc_time *tm)
return 0;
}
void rtc_set(struct rtc_time *tm)
int rtc_set(struct rtc_time *tm)
{
u8 buf[M41T62_DATETIME_REG_SIZE];
@ -123,8 +123,12 @@ void rtc_set(struct rtc_time *tm)
/* assume 20YY not 19YY */
buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100);
if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE))
if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) {
printf("I2C write failed in %s()\n", __func__);
return -1;
}
return 0;
}
void rtc_reset(void)

4
drivers/rtc/m48t35ax.c
View File

@ -87,7 +87,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar ccr; /* Clock control register */
uchar century;
@ -116,6 +116,8 @@ void rtc_set (struct rtc_time *tmp)
ccr = rtc_read(0);
ccr = ccr & 0x7F;
rtc_write(0, ccr);
return 0;
}
void rtc_reset (void)

4
drivers/rtc/max6900.c
View File

@ -107,7 +107,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
@ -124,6 +124,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (0x84, bin2bcd(tmp->tm_hour));
rtc_write (0x82, bin2bcd(tmp->tm_min ));
rtc_write (0x80, bin2bcd(tmp->tm_sec ));
return 0;
}
void rtc_reset (void)

8
drivers/rtc/mc13783-rtc.c
View File

@ -77,7 +77,7 @@ int rtc_get(struct rtc_time *rtc)
return 0;
}
void rtc_set(struct rtc_time *rtc)
int rtc_set(struct rtc_time *rtc)
{
u32 time, day, reg;
@ -86,7 +86,7 @@ void rtc_set(struct rtc_time *rtc)
slave = spi_setup_slave(1, 0, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return;
return -1;
}
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
@ -95,7 +95,7 @@ void rtc_set(struct rtc_time *rtc)
time %= 86400;
if (spi_claim_bus(slave))
return;
return -1;
reg = 0x2c000000 | day | 0x80000000;
spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day,
@ -106,6 +106,8 @@ void rtc_set(struct rtc_time *rtc)
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return -1;
}
void rtc_reset(void)

3
drivers/rtc/mc146818.c
View File

@ -105,7 +105,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
#ifdef RTC_DEBUG
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
@ -127,6 +127,7 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */
return 0;
}
void rtc_reset (void)

4
drivers/rtc/mcfrtc.c
View File

@ -68,7 +68,7 @@ int rtc_get(struct rtc_time *tmp)
return 0;
}
void rtc_set(struct rtc_time *tmp)
int rtc_set(struct rtc_time *tmp)
{
volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
@ -106,6 +106,8 @@ void rtc_set(struct rtc_time *tmp)
rtc->days = days;
rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min;
rtc->seconds = tmp->tm_sec;
return 0;
}
void rtc_reset(void)

6
drivers/rtc/mk48t59.c
View File

@ -185,7 +185,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar save_ctrl_a;
@ -210,6 +210,8 @@ void rtc_set (struct rtc_time *tmp)
save_ctrl_a &= ~RTC_CA_WRITE;
rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */
return 0;
}
void rtc_reset (void)
@ -225,7 +227,7 @@ void rtc_reset (void)
rtc_write(RTC_CONTROLB, control_b);
}
void rtc_set_watchdog(short multi, short res)
int rtc_set_watchdog(short multi, short res)
{
uchar wd_value;

4
drivers/rtc/mpc5xxx.c
View File

@ -88,7 +88,7 @@ int rtc_get (struct rtc_time *tmp)
/*****************************************************************************
* set time
*****************************************************************************/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800);
ulong time, date, year;
@ -129,6 +129,8 @@ void rtc_set (struct rtc_time *tmp)
udelay (1000);
rtc->tsr = time;
udelay (1000);
return 0;
}
/*****************************************************************************

4
drivers/rtc/mpc8xx.c
View File

@ -51,7 +51,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
ulong tim;
@ -65,6 +65,8 @@ void rtc_set (struct rtc_time *tmp)
immr->im_sitk.sitk_rtck = KAPWR_KEY;
immr->im_sit.sit_rtc = tim;
return 0;
}
void rtc_reset (void)

4
drivers/rtc/pcf8563.c
View File

@ -86,7 +86,7 @@ int rtc_get (struct rtc_time *tmp)
return rel;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
uchar century;
@ -104,6 +104,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (0x04, bin2bcd(tmp->tm_hour));
rtc_write (0x03, bin2bcd(tmp->tm_min ));
rtc_write (0x02, bin2bcd(tmp->tm_sec ));
return 0;
}
void rtc_reset (void)

6
drivers/rtc/pl031.c Executable file → Normal file
View File

@ -75,7 +75,7 @@ void rtc_reset(void)
/*
* Set the RTC
*/
void rtc_set(struct rtc_time *tmp)
int rtc_set(struct rtc_time *tmp)
{
unsigned long tim;
@ -84,7 +84,7 @@ void rtc_set(struct rtc_time *tmp)
if (tmp == NULL) {
puts("Error setting the date/time\n");
return;
return -1;
}
/* Calculate number of seconds this incoming time represents */
@ -92,6 +92,8 @@ void rtc_set(struct rtc_time *tmp)
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
RTC_WRITE_REG(RTC_LR, tim);
return -1;
}
/*

10
drivers/rtc/rs5c372.c
View File

@ -205,7 +205,7 @@ rtc_set (struct rtc_time *tmp)
rs5c372_enable();
if (!setup_done)
return;
return -1;
if(rtc_debug > 2) {
printf("rtc_set: tm_year = %d\n", tmp->tm_year);
@ -249,11 +249,15 @@ rtc_set (struct rtc_time *tmp)
buf[7] = bin2bcd(tmp->tm_year % 100);
ret = i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 8);
if (ret != 0)
if (ret != 0) {
printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
return -1;
}
} else {
return -1;
}
return;
return 0;
}
/*

10
drivers/rtc/rx8025.c
View File

@ -136,7 +136,11 @@ int rtc_get (struct rtc_time *tmp)
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
tmp->tm_hour = bcd2bin (hour & 0x3F);
else
tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
((hour & 0x20) ? 12 : 0);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
@ -154,7 +158,7 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@ -172,6 +176,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
return 0;
}
/*

4
drivers/rtc/s3c24x0_rtc.c
View File

@ -135,7 +135,7 @@ int rtc_get (struct rtc_time *tmp)
return 0;
}
void rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
uchar sec, min, hour, mday, wday, mon, year;
@ -167,6 +167,8 @@ void rtc_set (struct rtc_time *tmp)
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
return 0;
}
void rtc_reset (void)

4
drivers/rtc/x1205.c
View File

@ -134,7 +134,7 @@ int rtc_get(struct rtc_time *tm)
return 0;
}
void rtc_set(struct rtc_time *tm)
int rtc_set(struct rtc_time *tm)
{
int i;
u8 buf[8];
@ -168,6 +168,8 @@ void rtc_set(struct rtc_time *tm)
rtc_write(X1205_CCR_BASE + i, buf[i]);
rtc_write(X1205_REG_SR, 0);
return 0;
}
void rtc_reset(void)

35
drivers/usb/usb_ohci.c
View File

@ -109,6 +109,14 @@ static struct pci_device_id ohci_pci_ids[] = {
};
#endif
#ifdef CONFIG_PCI_EHCI_DEVNO
static struct pci_device_id ehci_pci_ids[] = {
{0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
/* Please add supported PCI EHCI controller ids here */
{0, 0}
};
#endif
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
#else
@ -1572,11 +1580,38 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
static int hc_reset (ohci_t *ohci)
{
#ifdef CONFIG_PCI_EHCI_DEVNO
pci_dev_t pdev;
#endif
int timeout = 30;
int smm_timeout = 50; /* 0,5 sec */
dbg("%s\n", __FUNCTION__);
#ifdef CONFIG_PCI_EHCI_DEVNO
/*
* Some multi-function controllers (e.g. ISP1562) allow root hub
* resetting via EHCI registers only.
*/
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
if (pdev != -1) {
u32 base;
int timeout = 1000;
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
writel (readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
base + EHCI_USBCMD_OFF);
while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
if (timeout-- <= 0) {
printf("USB RootHub reset timed out!");
break;
}
udelay(1);
}
} else
printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
#endif
if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
info("USB HC TakeOver from SMM");

3
drivers/usb/usb_ohci.h
View File

@ -195,6 +195,9 @@ struct ohci_regs {
} roothub;
} __attribute((aligned(32)));
/* Some EHCI controls */
#define EHCI_USBCMD_OFF 0x20
#define EHCI_USBCMD_HCRESET (1 << 1)
/* OHCI CONTROL AND STATUS REGISTER MASKS */

24
drivers/video/cfb_console.c
View File

@ -314,10 +314,10 @@ void console_cursor (int state);
#else
#define SWAP16(x) (x)
#define SWAP32(x) (x)
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
#define SHORTSWAP32(x) (x)
#else
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) )
#else
#define SHORTSWAP32(x) (x)
#endif
#endif
@ -932,12 +932,12 @@ int video_display_bitmap (ulong bmp_image, int x, int y)
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
FILL_15BIT_555RGB (cte.red, cte.green, cte.blue);
#else
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap (fb, xpos++, cte.red,
cte.green, cte.blue);
fb += 2;
#else
FILL_15BIT_555RGB (cte.red, cte.green, cte.blue);
#endif
}
bmap += padded_line;
@ -1006,12 +1006,12 @@ int video_display_bitmap (ulong bmp_image, int x, int y)
WATCHDOG_RESET ();
xcount = width;
while (xcount--) {
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]);
#else
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap (fb, xpos++, bmap[2],
bmap[1], bmap[0]);
fb += 2;
#else
FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]);
#endif
bmap += 3;
}
@ -1136,11 +1136,11 @@ void logo_plot (void *screen, int width, int x, int y)
*dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
break;
case GDF_15BIT_555RGB:
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap (dest, xpos++, r, g, b);
#else
*(unsigned short *) dest =
SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
#else
fill_555rgb_pswap (dest, xpos++, r, g, b);
#endif
break;
case GDF_16BIT_565RGB:

118
fs/jffs2/jffs2_1pass.c
View File

@ -268,6 +268,107 @@ static void put_fl_mem_nand(void *buf)
}
#endif
#if defined(CONFIG_CMD_ONENAND)
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <onenand_uboot.h>
#define ONENAND_PAGE_SIZE 2048
#define ONENAND_PAGE_SHIFT 11
#define ONENAND_PAGE_MASK (~(ONENAND_PAGE_SIZE-1))
#ifndef ONENAND_CACHE_PAGES
#define ONENAND_CACHE_PAGES 4
#endif
#define ONENAND_CACHE_SIZE (ONENAND_CACHE_PAGES*ONENAND_PAGE_SIZE)
static u8* onenand_cache;
static u32 onenand_cache_off = (u32)-1;
static int read_onenand_cached(u32 off, u32 size, u_char *buf)
{
u32 bytes_read = 0;
size_t retlen;
int cpy_bytes;
while (bytes_read < size) {
if ((off + bytes_read < onenand_cache_off) ||
(off + bytes_read >= onenand_cache_off + ONENAND_CACHE_SIZE)) {
onenand_cache_off = (off + bytes_read) & ONENAND_PAGE_MASK;
if (!onenand_cache) {
/* This memory never gets freed but 'cause
it's a bootloader, nobody cares */
onenand_cache = malloc(ONENAND_CACHE_SIZE);
if (!onenand_cache) {
printf("read_onenand_cached: can't alloc cache size %d bytes\n",
ONENAND_CACHE_SIZE);
return -1;
}
}
retlen = ONENAND_CACHE_SIZE;
if (onenand_read(&onenand_mtd, onenand_cache_off, retlen,
&retlen, onenand_cache) != 0 ||
retlen != ONENAND_CACHE_SIZE) {
printf("read_onenand_cached: error reading nand off %#x size %d bytes\n",
onenand_cache_off, ONENAND_CACHE_SIZE);
return -1;
}
}
cpy_bytes = onenand_cache_off + ONENAND_CACHE_SIZE - (off + bytes_read);
if (cpy_bytes > size - bytes_read)
cpy_bytes = size - bytes_read;
memcpy(buf + bytes_read,
onenand_cache + off + bytes_read - onenand_cache_off,
cpy_bytes);
bytes_read += cpy_bytes;
}
return bytes_read;
}
static void *get_fl_mem_onenand(u32 off, u32 size, void *ext_buf)
{
u_char *buf = ext_buf ? (u_char *)ext_buf : (u_char *)malloc(size);
if (NULL == buf) {
printf("get_fl_mem_onenand: can't alloc %d bytes\n", size);
return NULL;
}
if (read_onenand_cached(off, size, buf) < 0) {
if (!ext_buf)
free(buf);
return NULL;
}
return buf;
}
static void *get_node_mem_onenand(u32 off)
{
struct jffs2_unknown_node node;
void *ret = NULL;
if (NULL == get_fl_mem_onenand(off, sizeof(node), &node))
return NULL;
ret = get_fl_mem_onenand(off, node.magic ==
JFFS2_MAGIC_BITMASK ? node.totlen : sizeof(node),
NULL);
if (!ret) {
printf("off = %#x magic %#x type %#x node.totlen = %d\n",
off, node.magic, node.nodetype, node.totlen);
}
return ret;
}
static void put_fl_mem_onenand(void *buf)
{
free(buf);
}
#endif
#if defined(CONFIG_CMD_FLASH)
/*
@ -313,6 +414,11 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
return get_fl_mem_nand(off, size, ext_buf);
#endif
#if defined(CONFIG_CMD_ONENAND)
if (id->type == MTD_DEV_TYPE_ONENAND)
return get_fl_mem_onenand(off, size, ext_buf);
#endif
printf("get_fl_mem: unknown device type, using raw offset!\n");
return (void*)off;
}
@ -332,6 +438,11 @@ static inline void *get_node_mem(u32 off)
return get_node_mem_nand(off);
#endif
#if defined(CONFIG_CMD_ONENAND)
if (id->type == MTD_DEV_TYPE_ONENAND)
return get_node_mem_onenand(off);
#endif
printf("get_node_mem: unknown device type, using raw offset!\n");
return (void*)off;
}
@ -345,6 +456,13 @@ static inline void put_fl_mem(void *buf)
if (id->type == MTD_DEV_TYPE_NAND)
return put_fl_mem_nand(buf);
#endif
#if defined(CONFIG_CMD_ONENAND)
struct mtdids *id = current_part->dev->id;
if (id->type == MTD_DEV_TYPE_ONENAND)
return put_fl_mem_onenand(buf);
#endif
}
/* Compression names */

1
include/asm-arm/global_data.h
View File

@ -63,6 +63,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")

1
include/asm-avr32/global_data.h
View File

@ -54,6 +54,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")

1
include/asm-blackfin/global_data.h
View File

@ -64,6 +64,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")

1
include/asm-i386/global_data.h
View File

@ -57,6 +57,7 @@ typedef struct {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
extern gd_t *global_data;

1
include/asm-m68k/global_data.h
View File

@ -75,6 +75,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#if 0
extern gd_t *global_data;

1
include/asm-microblaze/global_data.h
View File

@ -55,6 +55,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")

1
include/asm-mips/global_data.h
View File

@ -57,6 +57,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")

1
include/asm-nios/global_data.h
View File

@ -48,6 +48,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7")

1
include/asm-nios2/global_data.h
View File

@ -47,6 +47,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15")

1
include/asm-ppc/global_data.h
View File

@ -180,6 +180,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")

1
include/asm-sh/global_data.h
View File

@ -47,6 +47,7 @@ typedef struct global_data
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")

1
include/asm-sparc/global_data.h
View File

@ -82,6 +82,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")

2
include/configs/ap325rxa.h
View File

@ -117,7 +117,7 @@
/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_EMPTY_INFO

2
include/configs/favr-32-ezkit.h
View File

@ -160,7 +160,7 @@
/* External flash on Favr-32 */
#if 0
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000

1
include/configs/socrates.h
View File

@ -410,6 +410,7 @@
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_PCI_OHCI 1
#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_OHCI_SWAP_REG_ACCESS 1

9
include/jffs2/load_kernel.h
View File

@ -28,9 +28,12 @@
#include <linux/list.h>
/* mtd device types */
#define MTD_DEV_TYPE_NOR 0x0001
#define MTD_DEV_TYPE_NAND 0x0002
#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor")
#define MTD_DEV_TYPE_NOR 0x0001
#define MTD_DEV_TYPE_NAND 0x0002
#define MTD_DEV_TYPE_ONENAND 0x0004
#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : \
(type == MTD_DEV_TYPE_ONENAND) ? "onenand" : "nor")
struct mtd_device {
struct list_head link;

2
include/rtc.h
View File

@ -53,7 +53,7 @@ struct rtc_time {
};
int rtc_get (struct rtc_time *);
void rtc_set (struct rtc_time *);
int rtc_set (struct rtc_time *);
void rtc_reset (void);
void GregorianDay (struct rtc_time *);

14
ppc_config.mk
View File

@ -23,3 +23,17 @@
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
PLATFORM_LDFLAGS += -n
#
# When cross-compiling on NetBSD, we have to define __PPC__ or else we
# will pick up a va_list declaration that is incompatible with the
# actual argument lists emitted by the compiler.
#
# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3]
ifeq ($(CROSS_COMPILE),powerpc-netbsd-)
PLATFORM_CPPFLAGS+= -D__PPC__
endif
ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
PLATFORM_CPPFLAGS+= -D__PPC__
endif