This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.
Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The IGEP SMARC AM335x is an industrial processor module with
following highlights:
o AM3352 TI processor (Up to AM3359)
o Cortex-A8 ARM CPU
o SMARC form factor module
o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
o WiFi a/b/g/n and Bluetooth v4.0 on-board
o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
o JTAG debug connector available
o Designed for industrial range purposes
Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
am33xx does not support OneNAND, but we need this define anyway
to let UBI SPL code compile.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.
To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only difference is to pass "DEVICE_TREE=stm32f769-disco".
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
This patch also removes the sdram/fmc clock enable from board specific
code.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
The symbol CONFIG_DRA7XX is needed for Kconfig conditions.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
In dram_init_banksize there seems to be a typo concerning
a plausibility check of the fdt.
Testing sc > 2 twice does not make any sense.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).
Add clock configuration of R40 SATA.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
For the consistent location of SoC-level Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
With 3f66149d9f we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup. On ARM however we largely relied on this call. Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location. Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d9f ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_DIAG
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_DIAG on some keymile configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_DEKBLOB
Note: This option does not seem to actually be enabled by any board.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply under SECURE_BOOT for mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than using CMD_CRAMFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CRAMFS
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CRAMFS
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CRAMFS for keymile]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CLK
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CLK on ARCH_ZYNQ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than using CMD_CBFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CBFS
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CBFS
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_BMODE
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make this default y and depend on mx5/6/7]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_BLOB
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add imply CMD_BLOB under CHAIN_OF_TRUST]
Signed-off-by: Tom Rini <trini@konsulko.com>
A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 /
CONFIG_MX53 being in Kconfig. Do so now.
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit adds support for HDMI output.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds support for DM I2C on sunxi platform. It can coexist
with old style sunxi I2C driver, because it is still used in SPL and
by some SoCs.
Because sunxi platform doesn't yet support DM clk, reset and pinctrl
driver, workaround is needed to enable clocks and set resets and
pinctrls. This is done by calling i2c_init_board() in board_init().
This means that CONFIG_I2Cx_ENABLE options needs to be correctly set
in order to use needed I2C controller.
Commit is based on the previous patch made by Philipp Tomsich
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
Tested on STM32f746-disco board
Similar commit:
f99993c108
Author: Matt Porter <mporter@konsulko.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs.
Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this
naming.
Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim
down the arch/arm/Kconfig level.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Almost all TI defconfigs enable this already, add this as a default
and remove the explicit assignment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are more and more cases where if we do not use gcc-6.0 or later we
run into problems where our binaries are too large for the targets.
Given the prevalence of gcc-6.0 or later toolchains at this point in
time, we give notice now that starting with v2018.01 we will require
gcc-6 (or later) for ARM.
Signed-off-by: Tom Rini <trini@konsulko.com>
Unfortunately a test for the PWM uclass was not included when it was
submitted. This was noticed when trying to add more functionality:
http://patchwork.ozlabs.org/patch/748172/
Add a simple test to get us started.
Signed-off-by: Simon Glass <sjg@chromium.org>
The name of the gpio bank under DM_GPIO appear to be a copy-paste error.
This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The register names and offset were not correct as per the TRM for OMAP3530
and OMAP3630. Correct the naing and offsets per the documentation
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Fixes the following problem:
zynq-uboot> run dfu_ram
Setting bus to 1
g_dnl_register: failed!, error: -19
The cause appears to be that the USB framework is looking for a usbotg aliases,
so add the alias to point to our USB device.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
As we have now V3s support in board code, the V3s DTSI file should also
be added.
Add also some CCU include headers to satisfy the DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Use - instead of @ for OPP tables
- Add input-delay properties to Cadence eMMC nodes
- Restore full license text because code-diff is annoying
- Fix NAND compatible strings
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SCP (System Control Processor) or what we call STM (Stand-by
MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20.
For these SoCs, show the information if STM is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This configuration is supposed to be used with ARM Trusted Firmware,
so the SYSTEM_RESET is implemented in BL31. Invoke PSCI instead of
U-Boot's own reset code because we need to coordinate with SCP
(System Control Processor) for the system-level power management.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is needed for HDMI, which will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.
It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.
This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 has the CPUCFG block at the same address as the A20.
Fix it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Each call of va_start must be matched by a call of va_end.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.
The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The Intel CPU name can have leading spaces. Remove them since they are not
useful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size
as header is appended to u-boot image. So header will also be
copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for the
header.
- Reduce the size of CAAM driver for SPL Blobification functions
and descriptors, that are not required at the time of SPL are
disabled. Further error code conversion to strings is disabled
for SPL build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
also defined.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The header address of PPA defined in Kconfig.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
BLOB feature is not required during SPL compilation.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
