Ruchika Gupta 668ec87f52 powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram ... For E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/ unlocks both L1 and L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2017-04-17 09:03:30 -07:00
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arc	board_f: Rename initdram() to dram_init()	2017-04-13 09:40:57 -04:00
arm	armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ	2017-04-17 09:03:30 -07:00
avr32	Remove various unused interrupt related code	2017-04-06 20:42:18 -04:00
m68k	spi: Zap cf_qspi driver and related code	2017-01-15 18:29:04 +01:00
microblaze	microblaze: Fix endif macro command	2017-02-10 13:59:36 +01:00
mips	board_f: Rename initdram() to dram_init()	2017-04-13 09:40:57 -04:00
nds32	Remove various unused interrupt related code	2017-04-06 20:42:18 -04:00
nios2	board_f: Rename initdram() to dram_init()	2017-04-13 09:40:57 -04:00
powerpc	powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram	2017-04-17 09:03:30 -07:00
sandbox	sandbox: Change CONFIG_SANDBOX_BITS_PER_LONG to hard-coded	2017-04-13 09:41:09 -04:00
sh	sh: generate position independent code for all platforms	2016-12-02 21:32:54 -05:00
x86	x86: Introduce minimal PMU driver for Intel MID platforms	2017-04-10 10:02:03 +08:00
xtensa	board_f: Rename initdram() to dram_init()	2017-04-13 09:40:57 -04:00
.gitignore	.gitignore: drop include/asm/proc from ignore pattern	2014-06-19 11:18:54 -04:00
Kconfig	OpenRISC: Remove	2017-04-05 13:52:34 -04:00