board_f: Rename initdram() to dram_init()

This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>

arch/arc/lib/cpu.c

@@ -28,3 +28,9 @@ int arch_early_init_r(void)
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+/* This is a dummy function on arc */
+int dram_init(void)
+{
+	return 0;
+}

arch/mips/mach-ath79/dram.c

@@ -11,7 +11,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int initdram(void)
+int dram_init(void)
 {
 	ddr_tap_tuning();
 	gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);

arch/mips/mach-pic32/cpu.c

@@ -110,7 +110,7 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-int initdram(void)
+int dram_init(void)
 {
 	ddr2_pmd_ungate();
 	ddr2_phy_init();

arch/mips/mach-pic32/include/mach/ddr.h

@@ -8,7 +8,7 @@
 #ifndef __MICROCHIP_PIC32_DDR_H
 #define __MICROCHIP_PIC32_DDR_H
 
-/* called by initdram() function */
+/* called by dram_init() function */
 void ddr2_phy_init(void);
 void ddr2_ctrl_init(void);
 phys_size_t ddr2_calculate_size(void);

arch/nios2/cpu/cpu.c

@@ -150,3 +150,9 @@ U_BOOT_DRIVER(altera_nios2) = {
 	.ops		= &altera_nios2_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
 };
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+	return 0;
+}

arch/powerpc/cpu/mpc5xxx/spl_boot.c

@@ -32,7 +32,7 @@ void board_init_f(ulong bootflag)
 	/*
 	 * On MPC5200, the initial RAM (and gd) is located in the internal
 	 * SRAM. So we can actually call the preloader console init code
-	 * before calling initdram(). This makes serial output (printf)
+	 * before calling dram_init(). This makes serial output (printf)
 	 * available very early, even before SDRAM init, which has been
 	 * an U-Boot priciple from day 1.
 	 */
@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram();
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -401,7 +401,7 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
-int initdram(void)
+int dram_init(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
@@ -413,7 +413,7 @@ int initdram(void)
 	return 0;
 }
 #else /* CONFIG_SYS_RAMBOOT */
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 

arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

@@ -403,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr)
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -2855,13 +2855,13 @@ static void test(void)
 #else /* CONFIG_SPD_EEPROM */
 
 /*-----------------------------------------------------------------------------
- * Function:	initdram
+ * Function:	dram_init
  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
  * 		The configuration is performed using static, compile-
  *		time parameters.
  * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned long val;
 

arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

@@ -987,20 +987,20 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
+ * dram_init.  Initializes the 440EPx/GPx DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_ranks[MAXDIMMS];
@@ -1014,7 +1014,7 @@ int initdram(void)
 	unsigned long cas_latency = 0;	/* to quiet initialization warning */
 	unsigned long dram_size;
 
-	debug("\nEntering initdram()\n");
+	debug("\nEntering dram_init()\n");
 
 	/*------------------------------------------------------------------
 	 * Stop the DDR-SDRAM controller.

arch/powerpc/cpu/ppc4xx/sdram.c

@@ -150,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-int initdram(void)
+int dram_init(void)
 {
 	ulong speed;
 	ulong sdtr1;
@@ -353,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *	 so this should be extended for other future boards
  *	 using this routine!
  */
-int initdram(void)
+int dram_init(void)
 {
 	int i;
 	int tr1_bank1;

arch/powerpc/cpu/ppc4xx/spl_boot.c

@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram();
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);

arch/xtensa/cpu/cpu.c

@@ -47,3 +47,8 @@ int arch_cpu_init(void)
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+int dram_init(void)
+{
+	return 0;
+}

board/Arcturus/ucp1020/spl.c

@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	initdram();
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/BuS/eb_cpu5282/eb_cpu5282.c

@@ -35,7 +35,7 @@ int checkboard (void)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	int size, i;
 

board/a3m071/a3m071.c

@@ -72,11 +72,11 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-int initdram(void)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;

board/a4m072/a4m072.c

@@ -68,12 +68,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-int initdram(void)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	uint svr, pvr;

board/amcc/acadia/memory.c

@@ -43,7 +43,7 @@ static void cram_bcr_write(u32 wr_val)
 	return;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	int i;
 	u32 val;

board/amcc/bamboo/bamboo.c

@@ -438,7 +438,7 @@ int checkboard(void)
 }
 
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = spd_sdram();
 

board/amcc/bubinga/bubinga.c

@@ -54,10 +54,10 @@ int checkboard(void)
 }
 
 /* -------------------------------------------------------------------------
-  initdram() reads EEPROM via I2c. EEPROM contains all of
+  dram_init() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
    ------------------------------------------------------------------------- */
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = spd_sdram();
 

board/amcc/sequoia/sdram.c

@@ -30,10 +30,10 @@ extern void denali_core_search_data_eye(void);
 
 /*************************************************************************
  *
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-int initdram(void)
+int dram_init(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);

board/amcc/walnut/walnut.c

@@ -73,10 +73,10 @@ int checkboard(void)
 }
 
 /*
- * initdram() reads EEPROM via I2c. EEPROM contains all of
+ * dram_init() reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = spd_sdram();
 

board/amcc/yosemite/yosemite.c

@@ -205,7 +205,7 @@ int checkboard(void)
 }
 
 /*************************************************************************
- *  initdram -- doesn't use serial presence detect.
+ *  dram_init -- doesn't use serial presence detect.
  *
  *  Assumes:    256 MB, ECC, non-registered
  *              PLB @ 133 MHz
@@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;

board/astro/mcf5373l/mcf5373l.c

@@ -27,7 +27,7 @@ int checkboard(void)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);

board/canmb/canmb.c

@@ -62,12 +62,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-int initdram(void)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;

board/cm5200/cm5200.c

@@ -97,7 +97,7 @@ static mem_conf_t* get_mem_config(int board_type)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-int initdram(void)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT

board/cobra5272/cobra5272.c

@@ -17,7 +17,7 @@ int checkboard (void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 

board/davedenx/aria/aria.c

@@ -18,7 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = fixed_sdram(NULL, NULL, 0);
 

board/dbau1x00/dbau1x00.c

@@ -13,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */

board/esd/mecp5123/mecp5123.c

@@ -62,7 +62,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
 

board/esd/pmc440/sdram.c

@@ -42,7 +42,7 @@ struct sdram_conf_s sdram_conf[] = {
 };
 
 /*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  */
 int initdram_by_rb(int rows, int banks)
 {
@@ -107,7 +107,7 @@ int initdram_by_rb(int rows, int banks)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t size;
 	int n;

board/esd/vme8349/vme8349.c

@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void ddr_enable_ecc(unsigned int dram_size);
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/b4860qds/ddr.c

@@ -176,7 +176,7 @@ found:
 	popts->cpo_sample = 0x3e;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/b4860qds/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_boot();

board/freescale/c29xpcie/spl.c

@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("TPL\n");

board/freescale/corenet_ds/ddr.c

@@ -260,7 +260,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/m5208evbe/m5208evbe.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m52277evb/m52277evb.c

@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize;
 

board/freescale/m5235evb/m5235evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);

board/freescale/m5249evb/m5249evb.c

@@ -31,7 +31,7 @@ int checkboard (void) {
 };
 
 
-int initdram(void)
+int dram_init(void)
 {
 	unsigned long	junk = 0xa5a59696;
 

board/freescale/m5253demo/m5253demo.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize = 0;
 

board/freescale/m5253evbe/m5253evbe.c

@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized

board/freescale/m5272c3/m5272c3.c

@@ -19,7 +19,7 @@ int checkboard (void) {
 	return 0;
 	};
 
-int initdram(void)
+int dram_init(void)
 {
 	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 

board/freescale/m5275evb/m5275evb.c

@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
 	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);

board/freescale/m5282evb/m5282evb.c

@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize, i, dramclk;
 

board/freescale/m53017evb/m53017evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m5329evb/m5329evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m5373evb/m5373evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m54418twr/m54418twr.c

@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize;
 

board/freescale/m54451evb/m54451evb.c

@@ -26,7 +26,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF

board/freescale/m54455evb/m54455evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF

board/freescale/m547xevb/m547xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);

board/freescale/m548xevb/m548xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);

board/freescale/mpc5121ads/mpc5121ads.c

@@ -95,7 +95,7 @@ int is_micron(void){
 	return(ismicron);
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 msize = 0;
 	/*

board/freescale/mpc8308rdb/sdram.c

@@ -65,7 +65,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/freescale/mpc8313erdb/mpc8313erdb.c

@@ -134,7 +134,7 @@ void board_init_f(ulong bootflag)
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
 	timer_init();
-	initdram();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }

board/freescale/mpc8313erdb/sdram.c

@@ -97,7 +97,7 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;

board/freescale/mpc8315erdb/mpc8315erdb.c

@@ -222,7 +222,7 @@ void board_init_f(ulong bootflag)
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
 	timer_init();
-	initdram();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }

board/freescale/mpc8315erdb/sdram.c

@@ -92,7 +92,7 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/freescale/mpc8323erdb/mpc8323erdb.c

@@ -70,7 +70,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc832xemds/mpc832xemds.c

@@ -90,7 +90,7 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc8349emds/mpc8349emds.c

@@ -48,7 +48,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	phys_size_t msize = 0;

board/freescale/mpc8349itx/mpc8349itx.c

@@ -118,7 +118,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif				/* CONFIG_PCI */
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc837xemds/mpc837xemds.c

@@ -218,7 +218,7 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -62,7 +62,7 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-int initdram(void)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -118,7 +118,7 @@ int checkboard(void)
 }
 
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -39,7 +39,7 @@ int checkboard(void)
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/p1010rdb/spl.c

@@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("\nTertiary program loader running in sram...");
 #else

board/freescale/p1022ds/spl.c

@@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	initdram();
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p1_p2_rdb_pc/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	initdram();
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p2041rdb/ddr.c

@@ -118,7 +118,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/t102xqds/ddr.c

@@ -169,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t102xqds/spl.c

@@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t102xrdb/ddr.c

@@ -229,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t102xrdb/spl.c

@@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t1040qds/ddr.c

@@ -117,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t104xrdb/ddr.c

@@ -120,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t104xrdb/spl.c

@@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xqds/ddr.c

@@ -104,7 +104,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t208xqds/spl.c

@@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xrdb/ddr.c

@@ -97,7 +97,7 @@ found:
 	popts->cpo_sample = 0x54;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t208xrdb/spl.c

@@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4qds/ddr.c

@@ -112,7 +112,7 @@ found:
 	popts->cpo_sample = 0x63;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t4qds/spl.c

@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4rdb/ddr.c

@@ -105,7 +105,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t4rdb/spl.c

@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	initdram();
+	dram_init();
 
 	mmc_boot();
 }

board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c

@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Does not set gd->ram_size here */
 

board/gaisler/gr_ep2s60/gr_ep2s60.c

@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Does not set gd->ram_size here */
 

board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c

@@ -9,7 +9,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Does not set gd->ram_size here */
 

board/gaisler/grsim/grsim.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Does not set gd->ram_size here */
 

board/gaisler/grsim_leon2/grsim_leon2.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-int initdram(void)
+int dram_init(void)
 {
 	/* Does not set gd->ram_size here */
 

board/gdsys/mpc8308/sdram.c

@@ -66,7 +66,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/ids/ids8313/ids8313.c

@@ -119,7 +119,7 @@ static int setup_sdram(void)
 	return msize;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	fsl_lbc_t *lbc = &im->im_lbc;

board/ifm/ac14xx/ac14xx.c

@@ -310,7 +310,7 @@ u32 sdram_init_seq[] = {
 	/* EMPTY, optional, we don't do it */
 };
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
 				   ARRAY_SIZE(sdram_init_seq));

board/ifm/o2dnt2/o2dnt2.c

@@ -62,11 +62,11 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-int initdram(void)
+int dram_init(void)
 {
 	struct mpc5xxx_mmap_ctl *mmap_ctl =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;

board/imgtec/boston/ddr.c

@@ -12,7 +12,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int initdram(void)
+int dram_init(void)
 {
 	u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
 

board/imgtec/malta/malta.c

@@ -85,7 +85,7 @@ static enum sys_con malta_sys_con(void)
 	}
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = CONFIG_SYS_MEM_SIZE;
 

board/imgtec/xilfpga/xilfpga.c

@@ -14,7 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* initialize the DDR Controller and PHY */
-int initdram(void)
+int dram_init(void)
 {
 	/* MIG IP block is smart and doesn't need SW
 	 * to do any init */

board/inka4x0/inka4x0.c

@@ -74,12 +74,12 @@ static void sdram_start (int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile struct mpc5xxx_mmap_ctl *mm =
 		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;

board/intercontrol/digsy_mtc/digsy_mtc.c

@@ -74,12 +74,12 @@ static void sdram_start(int hi_addr)
 #endif
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
  */
 
-int initdram(void)
+int dram_init(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;

board/ipek01/ipek01.c

@@ -75,12 +75,12 @@ static void sdram_start (int hi_addr)
 }
 
 /*
- * ATTENTION: Although partially referenced initdram does NOT make real
+ * ATTENTION: Although partially referenced dram_init does NOT make real
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
 
-int initdram(void)
+int dram_init(void)
 {
 	struct mpc5xxx_mmap_ctl *mmap_ctl =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;