This is needed for having access to the devices below this bus, most
important is uart and boot-device (spi, mmc, ...) in SPL stage.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
The Shared Memory Manager driver implements an interface for allocating
and accessing items in the memory area shared among all of the
processors in a Qualcomm platform.
Adapted from the Linux driver (4.17)
Changes from the original Linux driver:
* Removed HW spinlock mechanism, which is irrelevant
in U-boot particualar use case, which is just reading from the smem.
* Adapted from Linux driver model to U-Boot's.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Current implementation of find_next_zero_bit() is incompatible with arm64.
Hence fix it by using BITS_PER_LONG define instead of constants and
use generic ffz() implementation.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
This adds platform code for the FriendlyElec NanoPi K2 board based on a
Meson GXBB (S905) SoC with the Meson GXBB configuration.
This initial submission only supports:
- UART
- MMC/SDCard
- Ethernet
- Reset Controller
- Clock controller
Cc: Yuefei Tan <yftan@friendlyarm.com>
Signed-off-by: Thomas McKahan <tonymckahan@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The function set_default_env() sets the hashtable flags for import_r().
Formally set_default_env() doesn't accept flags from its callers. In
practice the caller can (un)set the H_INTERACTIVE flag, but it has to be
done using the first character of the function's string argument. Other
flags like H_FORCE can't be set by the caller.
Change the function to accept flags argument. The benefits are:
1. The caller will have to explicitly set the H_INTERACTIVE flag,
instead of un-setting it using a special char in a string.
2. Add the ability to propagate flags from the caller to himport(),
especially the H_FORCE flag from do_env_default() in nvedit.c that
currently gets ignored for "env default -a -f" commands.
3. Flags and messages will not be coupled together. A caller will be
able to set flags without passing a string and vice versa.
Please note:
The propagation of H_FORCE from do_env_default() does not introduce any
functional changes, because currently himport_r() is set to destroy the
old environment regardless if H_FORCE flag is set or not. More changes
are needed to utilize the propagation of H_FORCE.
Signed-off-by: Yaniv Levinsky <yaniv.levinsky@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
commit 4aba5fb857 ("arm: zynq: Rework FPGA initialization")
moved FPGA initialization from board_init() to arch_early_init_r(),
which is not called as part of the SPL
Fix this by calling arch_early_init_r() in the spl_board_init()
function, so the FPGA is correctly initialized
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of internal memory. This
configuration has only required qspi flash support and it
uses DCC as serial.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch renames the routine fdtdec_setup_memory_size()
to fdtdec_setup_mem_size_base() as it now fills the
mem base as well along with size.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.
GPIO reset is handled via sysreset with adding this fragment to DT.
gpio-restart {
compatible = "gpio-restart";
gpios = <&reset_gpio 0 0 0>;
/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};
hard-reset-gpio property is not documented and also handled.
Conversion is required.
Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is only one chipselect on each connector.
Define it directly in board dts file.
There should be an option to use more chipselects via gpios.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Timer needs to be converted to DM but as of now it can't be called so
early because intc controller is not ready. Call it later in board_r.c.
Before this patch timer_init is called twice which is wrong.
The patch is blocking initialization before relocation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no reason not to use default ioremap/iounmap io functions.
The patch remove Microblaze macros.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
authenticated or encrypted or both authenticated and encrypted
image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
image back to DDR as per destination address. The image has
to be encrypted using xilinx bootgen tool and to get only the
encrypted image from tool use -split option while invoking
bootgen.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on
ZynqMP (PS init for short). The current logic to locate this file for
both platforms is:
1. if a board-specific file exists in
board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c
then use it
2. otherwise use board/xilinx/zynq/ps?_init_gpl.c
In the latter case the file does not exist in the U-Boot sources and
must be copied in the source tree from the outside before starting the
build. This is typical when it is generated from Xilinx tools while
developing a custom hardware. However making sure that a
board-specific file is _not_ found (and used) requires some trickery
such as removing or overwriting all PS init files (e.g.: the current
meta-xilinx yocto layer).
This generates a few problems:
* if the source tree is shared among different out-of-tree builds,
they will pollute (and potentially corrupt) each other
* the source tree cannot be read-only
* any buildsystem must add a command to copy the PS init file binary
* overwriting or deleting files in the source tree is ugly as hell
Simplify usage by allowing to pass the path to the desired PS init
file in kconfig variable XILINX_PS_INIT_FILE. It can be an absolute
path or relative to $(srctree). If the variable is set, the
user-specified file will always be used without being copied
around. If the the variable is left empty, for backward compatibility
fall back to the old behaviour.
Since the issue is the same for Zynq and ZynqMP, add one kconfig
variable in a common place and use it for both.
Also use the new kconfig help text to document all the ways to give
U-Boot the PS init file.
Build-tested with all combinations of:
- platform: zynq or zynqmp
- PS init file: from XILINX_PS_INIT_FILE (absolute, relative path,
non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/
- building in-tree, in subdir, in other directory
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Libretech ALL-H3-CC has a high density connector for attaching
an eMMC module. The module form factor and connection is specific
to Libretech, and has provisions for split vmmc/vqmmc (core and I/O)
voltage supplies, but this board does not wire the vqmmc side. The
H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either.
Only 3.3V is supported. A specific module that ties vqmmc to vmmc,
with both at 3.3V, must be used.
Given that a) eMMC is not designed to be hotplugged, b) power is
always provided on the pins, and c) MMC controllers can deal with
missing cards, we can enable this by default. If a module is attached
it will be picked up by the system.
The device tree change was also submitted to the Linux Kernel and
has already been queued up for 4.19.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds qspi driver support for all ZynqMP ZCU102
boards.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Enable the gigabit ethernet for the Bananapi M2 Ultra board.
Tested on BananaPi M2 Berry (R40), custom board (V40)
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Add a device tree node for the Allwinner R40/V40 GMAC gigabit
ethernet interface.
The R40 SoC does not use the syscon register for GMAC settings.
The gigabit ethernet interface can only be routed to a fixed set of
pins.
Updated to match the Linux kernel's device tree.
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Use the driver model for MMC and SATA, in preparation for CONFIG_BLK
defaulting to y.
Tested on A10 Cubieboard.
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When the defconfig for the SoPine baseboard was added, there wasn't any
proper DT for the board yet, so we used the Pine64 DT as a placeholder.
Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use
them in our defconfig.
This is as of v4.18-rc3, exactly Linux commit:
commit 7d556bfc49adddf2beb0d16c91945c3b8b783282
Author: Jagan Teki <jagannadh.teki@gmail.com>
Date: Mon Dec 4 10:23:07 2017 +0530
arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Update the .dts file for the various boards with an Allwinner H3 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit 721afaa2aeb860067decdddadc84ed16f42f2048 (HEAD)
Merge: 7c00e8ae041b 87815dda5593
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Mon Jun 11 17:57:38 2018 -0700
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
This also includes the OrangePi Zero .dts, which technically has an
Allwinner H2+ SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Update the .dts file for the various boards with an Allwinner H5 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit af5d05bdc99c211729cba0a3d5417bccfa308caf
Author: Neil Armstrong <narmstrong@baylibre.com>
Date: Tue Apr 24 13:47:14 2018 +0200
arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Update the device tree files from the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit 55c5ba5e49a0a124ed416880e8227b493474495e
Author: Chen-Yu Tsai <wens@csie.org>
Date: Tue Apr 24 19:34:22 2018 +0800
arm64: dts: allwinner: h5: Add cpu0 label for first cpu
Since the H3 and H5 are very similar (aside from the actual ARM cores),
they share most the SoC .dtsi and thus have to be updated together.
One tiny change is the removal of the "arm/" prefix from the include
path in the sun50i-h5.dtsi, which is needed because we don't share the
same sophisticated DT directory layout of Linux.
Also we need to fix up the board .dts files already, since the .dtsi
removes some pins, so the .dts can't reference them anymore. This is to
maintain bisectability.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Update the .dts files for the various boards with an Allwinner A64 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit 818668055c9d588c9a9d151e3b258ed1adacba0b
Author: Jagan Teki <jagan@amarulasolutions.com>
Date: Mon Apr 23 12:02:39 2018 +0530
arm64: dts: allwinner: a64: bananapi-m64: add usb otg
It updates the existing DT files, adds the newly added axp803.dtsi and
removes our temporary kludge file to get Ethernet support in U-Boot.
I left the amarula-relic alone, as this DT has not reached mainline yet.
The changes are not critical anyway, and the next sync will fix this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Updates the device tree file from the the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit c1cff65f9b16b31e731e2e75bbe06638c86e1996
Author: Harald Geyer <harald@ccbib.org>
Date: Thu Mar 15 16:25:08 2018 +0000
arm64: dts: allwinner: a64: add simplefb for A64 SoC
This also pulls in the newly required include files for the clock and
reset bindings, also removes the now redundant part from our
*-u-boot.dtsi overlay file.
I kept the PWM node from U-Boot, as we recently gained this explicitly
for U-Boot's own usage and I don't want to regress here. This node is in
the queue for mainline Linux already, so the next sync will make it all
equal again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
CONFIG_SPL_RESET_SUPPORT has been renamed to CONFIG_SPL_DM_RESET, update
this Kconfig file.
Fixes: bfc6bae8fa ("reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Fix compilation warning when enable CONFIG_DEBUG_UART.
arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’:
arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration]
debug_uart_init();
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
MCR instruction only available in ARM 32-bit. So, compile MCR instruction
when ARM 32-bit is enabled.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get
memory size from DT. So, we need to update memory size in memory node.
Otherwise, it cause U-boot hang.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Make sure the ARM ACTLR register has correct configuration, otherwise
the Linux kernel refuses to boot. In particular, the "Write Full Line
of Zeroes" bit must be cleared.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
The SPL can also parse the DRAM configuration node to figure out the
memory layout, make sure it is available.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Pull the DRAM size from DT instead of hardcoding it into U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Add do_bridge_reset() function for Arria 10, it is required by misc.c.
arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
make[1]: *** [u-boot] Error 1
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add build support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Conflicts:
arch/arm/Kconfig
arch/arm/mach-socfpga/Kconfig
Add timer support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add mailbox support for Stratix SoC
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add misc support such as EMAC and cpu info printout for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add support for loading U-Boot on the Broadcom 7445 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Remove empty #ifdef/#ifndef..#endif blocks where the configuration they
guarded has been completely removed.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET, so can use
CONFIG_IS_ENABLED(DM_RESET) checking in reset.h later.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds uCRobotics Bubblegum-96 board support. This board is
one of the 96Boards Consumer Edition platform based on Actions Semi
S900 SoC.
Features:
- Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
- 2GiB RAM
- 8GiB eMMC, uSD slot
- WiFi, Bluetooth and GPS module
- 2x Host, 1x Device USB port
- HDMI
- 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
U-Boot will be loaded by ATF at EL2 execution level. Relevant driver
support will be added in further commits.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit adds Actions Semi OWL SoC family support with S900 as the
first target SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.
Fixes: 5ff8e54888 ("sunxi: improve throughput
in the sunxi_mmc driver")
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
The various Aries Embedded boards have been orphaned for a year and no
one has come forward to take care of them. Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
On x86 traditional E820 table is used to pass the memory information
to kernel. With EFI loader we can build the EFI memory map from it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.
If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This adds the scsi command to coreboot and qemu, to be in consistent
with other x86 targets.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On a 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53
to fix the problem.
With this patch applied the kernel reports:
CPU0: Spectre v2: using BPIALL workaround
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Enable CVE-2017-5715 option to set the IBE bit. This enables kernel
workarounds necessary for the said CVE.
With this enabled, Linux reports:
CPU0: Spectre v2: using BPIALL workaround
This workaround may need to be re-applied in OS environment around low
power transition resume states where context of ACR would be lost (off-mode
etc).
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr
function to setup the bits, we are able to override the settings.
Without this enabled, Linux kernel reports:
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
With this enabled, Linux kernel reports:
CPU0: Spectre v2: using ICIALLU workaround
NOTE: This by itself does not enable the workaround for CPU1 (on
OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB)
needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to
be done unconditionally for Cortex-A15 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.
NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the
right locations.
c) This workaround applies to only the boot processor. It is important
to apply workaround as necessary (context-save-restore) around low
power context loss OR additional processors as necessary in either
firmware support OR elsewhere in OS.
[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
for BPIALL to be functional on Cortex-A8 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.
NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the right
locations.
c) This workaround applies to only the boot processor. It is important
to apply workaround as necessary (context-save-restore) around low
power context loss OR additional processors as necessary in either
firmware support OR elsewhere in OS.
[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This patch update the USB PHY index for Allwinner H3.
Same change[1] initially sent, by 'Chen-Yu Tai' but missed
to apply due to recursive version changes on the same series.
[1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
fdt_file is looking for imx6ul-geam-kit.dtb but Linux
has imx6ul-geam.dtb, since Linux skipped -kit on file name
by below commit.
"ARM: dts: imx6ul-geam: Skip suffix -kit from dts name"
(sha1: 182de5ebce71e469cfa686fcdf08c9cbe11ece97)
So, due to this mismatch U-Boot failed to pick the
proper dtb which eventually break the Linux boot.
This patch fixed this mismatch by
- renaming dts files
- update config option to use new dtb file
- update fdt_file to new dtb file name
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
At present in dram_init_banksize() it ignores conventional memory
above 4GB. This leads to wrong DRAM size is printed during boot.
Remove such limitation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit bb0bb91cf0 ("efi_stub: Use efi_uintn_t"), EFI x86
64-bit payload does not work anymore. The call to GetMemoryMap()
in efi_stub.c fails with return code EFI_INVALID_PARAMETER. Since
the payload itself is still 32-bit U-Boot, efi_uintn_t gets wrongly
interpreted as int, but it should actually be long in a 64-bit EFI
environment.
This changes the x86 __kernel_size_t conditionals to use compiler
provided defines instead. That way we always adhere to the build
environment we're in and the definitions adjust automatically.
Fixes: bb0bb91cf0 ("efi_stub: Use efi_uintn_t")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For boards that don't route serial port pins out, it's quite common
to attach a USB keyboard as the input device, along with a monitor.
However USB is not automatically started in the generic efi payload
codes. This uses a payload specific last_stage_init() to start the
USB bus, so that a USB keyboard can be used on the U-Boot shell.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
car.o can only be used with start.o, not with start64.o.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that the clock-frequency information has been moved to the
driver, more DT sync is possible.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
cpu_cmd() is reading cpu number via simple_strtoul() which is always
unsigned type.
Platform code implementations are not expecting that nr can be negative
and there is not checking in the code for that too.
This patch is using u32 type for cpu number to make sure that platform
code get proper value range.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add option to the booti_setup() which indicates to it that the caller
requires the image to be relocated to the beginning of the RAM and
that the information whether the image can be located anywhere in RAM
at 2 MiB aligned boundary or not is to be ignored. This is useful ie.
in case the Image is wrapped in another envelope, ie. fitImage and not
relocating it but moving it would corrupt the envelope.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Chen <bin.chen@linaro.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-By: Bin Chen <bin.chen@linaro.org>
Add regulator nodes and pinmux settings to the SDHI3 on E3 Ebisu
and enable HS200 mode on it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Both the RAVB and SH ether driver now support parsing the PHY reset
GPIOs from both the PHY nodes and the MAC nodes, move the reset GPIOs
back into the PHY nodes to minimize DT difference between U-Boot and
Linux.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The current state of RAVB driver expects the PHY reset GPIO in the
RAVB mode, move it back from the PHY node to avoid breakage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
When CMD_GPIO is enabled the command 'gpio status -a' can cause
a hang or reboot if GPIO banks are not enabled, because it scans
all banks. This patch enables all GPIO banks so 'gpio status -a'
can fully execute.
Signed-off-by: Adam Ford <aford173@gmail.com>
When an exception or interrupt occurs the link register (LR) may
contain the source of the exception, although we do not print the
value it may still be extracted with a debugger. When in SPL we
loop on getting and exception, but use a linking branch, which
over-writes the LR value, use a regular branch instruction here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Follow Linux commit 10b62a2f785a (".gitignore: move *.dtb and *.dtb.S
patterns to the top-level .gitignore").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch prevents from the situation where we may end up with garbage
displayed on the LCD panel.
Such situation occurs when one performs "reboot -f" in Linux and then
stop in U-boot (or observe the garbage on the screen during boot up).
To prevent from such situation - the PWM pin is configured as GPIO and set
to LOW.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If many values differ from the defaults, overriding the full table
is simpler and more space efficient than tweaking it through
mxs_adjust_memory_params().
Signed-off-by: Mans Rullgard <mans@mansr.com>
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode,
it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
[fabio: adapted to U-Boot mainline codebase and make checkpatch happy]
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Currently when EFI application boots, it says:
CPU: x86_64, vendor <invalid cpu vendor>, device 0h
Fix this by calling x86_cpu_init_f() in arch_cpu_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To avoid confusion, let's rename the efi-x86 target to efi-x86_app.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This turns on the EFI framebuffer driver support so that a graphics
console can be of additional help.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic EFI payload support, drop EFI-specific test
logics in BayTrail Kconfig and codes, and all BayTrail boards too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic EFI payload support for all x86 boards,
drop the QEMU-specific one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is possible to create a generic EFI payload for all x86 boards.
The payload is configured to include as many generic drivers as
possible. All stuff that touches low-level initialization are not
allowed as such is the EFI BIOS's responsibility. Platform specific
drivers (like gpio, spi, etc) are not included.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds arch_cpu_init() to the payload codes, in preparation for
supporting a generic efi payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present the EFI application and payload support codes in the x86
directory is distributed in a hybrid way. For example, the Kconfig
options for both app and payload are in arch/x86/lib/efi/Kconfig,
but the source codes in the same directory get built only for
CONFIG_EFI_STUB.
This refactors the codes by consolidating all the EFI support codes
into arch/x86/cpu/efi, just like other x86 targets.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
UEFI specifies the calling convention used in Microsoft compilers;
first arguments of a function are passed in (%rcx, %rdx, %r8, %r9).
All other compilers use System V ABI by default, passing first integer
arguments of a function in (%rdi, %rsi, %rdx, %rcx, %r8, %r9).
These ABI also specify different sets of registers that must be preserved
across function calls (callee-saved).
GCC allows using the Microsoft calling convention by adding the ms_abi
attribute to a function declaration.
Current EFI implementation in U-Boot specifies EFIAPI for efi_main()
in the test apps but uses default calling convention in lib/efi.
Save efi_main() arguments in the startup code on x86_64;
use EFI calling convention for _relocate() on x86_64;
consistently use EFI calling convention for efi_main() everywhere.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Fix warning when compiling cherryhill.dts with latest DTC:
"Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property"
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Orange Pi Zero Plus is an open-source single-board computer
using the Allwinner H5 SOC.
H5 Orangepi Zero Plus has
- Quad-core Cortex-A53
- 512MB DDR3
- micrSD slot
- 16MBit SPI Nor flash
- Debug TTL UART
- 1GBit/s Ethernet (RTL8211E)
- Wifi (RTL8189FTV)
- USB 2.0 Host
- USB 2.0 OTG + power supply
The device tree file is copied from the Linux kernel 4.17.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Orange Pi R1 is an open-source single-board computer using the
Allwinner H2+ SOC.
H2+ Orange Pi R1 has
- Quad-core Cortex-A7
- 256MB DDR3
- micrSD slot
- 128MBit SPI Nor flash
- Debug TTL UART
- 100MBit/s Ethernet (H2+)
- 100MBit/s Ethernet (RTL8152B)
- Wifi (RTL8189ETV)
- USB 2.0 OTG + power supply
This board is very similar to the Orange Pi Zero.
The device tree file is copied from the Linux kernel 4.17.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add EtherAVB PHY reset on V3M Eagle to let the AVB driver unreset the PHY.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add EtherAVB pinmux node on V3M Eagle to set the pinmux configuration.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add device tree nodes for the Renesas RPC HF/QSPI controller
to R8A77990 E3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
There should be return value check from zynqmp_mmio_read() in
zynqmp_mmio_rawwrite() to make sure that errors are propagated properly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dtc is showing some warnings and this change was also done in
the Linux kernel as "Input: gpio-keys - clean up device tree binding
example"
with this fragment in commit message
"Drop #address-cells and #size-cells, which are not required by the
gpio-keys binding documentation, as button sub-nodes are not devices."
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch splits the current mini emmc configuration into emmc0
and emmc1 configurations because emmc is probed at boot time and on
systems which have only one interface mini configuration is failing on
unused interface. This patch also adds required clock node in dts and
enables CONFIG_MMC_SDHCI_ZYNQ through defconfig.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
A few minor fixes for the release:
- Compile fixes
- HI20 relocations for RISC-V
- Fix bootefi without load path
- Fix Runtime Services with certain compilers
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-06-14
A few minor fixes for the release:
- Compile fixes
- HI20 relocations for RISC-V
- Fix bootefi without load path
- Fix Runtime Services with certain compilers
We currently handle the UEFI runtime reset / power off case handling via
a switch statement. Compilers (gcc in my case) may opt to handle these via
jump tables which they may conveniently put into .rodata which is not part
of the runtime section, so it will be unreachable when executed.
Fix this by just converting the switch statement into an if/else statement.
It produces smaller code that is faster and also correct because we no
longer refer .rodata from efi runtime code.
Reported-by: Andreas Färber <aferber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.17.0
This will enable USB on Amlogic Meson GXL Boards like Khadas VIM, P212 or
LibreTech-CC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The "intel,pirq-link" property in Intel IRQ router's dt bindings
has two cells, where the second one represents the number of PIRQ
links on the platform. However current driver does not parse this
information from device tree. This adds the codes to do the parse
and save it for future use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Attempting to use a toolchain that is preconfigured to generate code
for the 32-bit architecture (i386), for example, the i386-linux-gcc
toolchain on kernel.org, to compile the 64-bit EFI payload does not
build. This updates the makefile fragments to ensure '-m64' is passed
to toolchain when building the 64-bit EFI payload stub codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pinctrl_ich6 driver is currently unconditionally built for all
x86 boards. Let's use a Kconfig option to control the build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
LINK_V2N and LINK_N2V are currently defines, so they cannot handle
complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use
the common one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board,
so that SMP can be supported too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this 206ax cpu driver is only built when FSP is not used.
This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It turns out that like Braswell, Intel FSP for IvyBridge requires
SPI controller settings to be locked down, as the U-Boot ICH SPI
driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Panther Point chipset connected to Ivybridge has xHC integrated,
imply it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The guaranteed vid bit ranges in IACORE_VIDS MSR is actually
[22:16]. This corrects the comment for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The helios4 is built on the SolidRun Armada 38x SOM.
The port os based on the ClearFog board, using information from
https://github.com/helios-4/u-boot-marvell as well as dtb input
from https://github.com/helios-4/linux-marvell
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE
MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
[yorks: rebase and fix SPDX tag]
[yorks: fix board/freescale/ls1012afrdm/Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
PPA firmware and header address may vary depending upon different
boards, configure ppa firmware and header address in board specific
Kconfig.
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The lowlevel_init function uses r4 and r6 without preserving their
values as required by the AAPCS. Use r0 and r2 instead as these
are call-clobbered.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Since commit 0e373c0ade ("spl: add SPL_RESET_SUPPORT"),
reset is supported in SPL, enable this flag for STM32F SoCs family.
This allows to remove a specific case in RCC mfd driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This is a series of line cards for Allied Telesis's SBx8100 chassis
switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16
and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The mach/config.h file would helpfully define CONFIG_SYS_I2C and
CONFIG_SYS_I2C_MVTWSI if CONFIG_CMD_I2C was defined by the board. This
conflicts with the way DM_I2C works. As a transitional measure don't
automatically define these if CONFIG_DM_I2C is defined. It should be
possible to remove this once all kirkwood boards are migrated to DM.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch shows how to enable driver model support for the LS-CHLv2 and
LS-XHL boards.
There are a couple of open questions:
- do I need the u-boot,dm-pre-reloc tags in the device tree?
- should mach/config.h define CONFIG_DM_SEQ_ALIAS?
- how can we split this patch or are there any other pending patches
which does the same and I didn't catch these.
This patch is based on the http://git.denx.de/u-boot-marvell.git (master
branch) and needs the following patches, which are still pending:
https://patchwork.ozlabs.org/patch/909618/https://patchwork.ozlabs.org/patch/909617/https://patchwork.ozlabs.org/patch/909973/
Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
This switches the clearfog boards to use DM based gpio and i2c
drivers. The io expanders are configured via their device-tree
entries.
Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: add DT i2c aliases]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Some QCA988x based modules presence is not detected by the SERDES lanes,
so force this detection which will trigger the LTSSM state machine to
negotiate link.
An example of such a card is WLE900VX.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
u-boot,dm-pre-reloc was missing from pinctrl and it's
children node. causing failure to configure pin mux
before relocation.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
This undocumented function relies on arch-specific code to declare a nop
weak version. Add the weak function in common code instead to avoid having
to duplicate the same function in each arch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
The EFI loader code requires certain linker sections to exist. Add these
for sandbox so that the EFI loader code will link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Add an implementation of setjmp() and longjmp() which rely on the
underlying host C library. Since we cannot know how large the jump buffer
needs to be, pick something that should be suitable and check it at
runtime. At present we need access to the underlying struct as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
The UEFI spec mandates that unaligned memory access should be enabled if
supported by the CPU architecture.
This patch implements the function unaligned_access() to reset the aligned
access flag in the system control register (SCTLR). It is called when the
bootefi command is invoked.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: fix SPDX identifier]
Signed-off-by: Alexander Graf <agraf@suse.de>
The efi selftest and the hello application require CRT0 and RELOC to be
built.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Variables EFI_RELOC and EFI_CRT0 have to be defined to build the
EFI unit tests. This patch ensures this for the x86 architecure.
If we compile with EFI_STUB, the bitness depends on CONFIG_EFI_STUB_64BIT.
Otherwise the bitness depends on CONFIG_X86_64.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Import the R8A77990 and Ebisu DTS from linux-next to get the latest
version. This makes AVB ethernet work in U-Boot since the ethernet
node is now present in DT, as well as GPIOs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Basic support for the Renesas Ebisu board based on R-Car E3:
- Memory,
- Main crystal,
- Serial console,
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: rebase and add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
- PSCI
- CPU (single)
- Cache controller
- Main clocks and controller
- Interrupt controller
- Timer
- PMU
- Reset controller
- Product register
- System controller
- UART for console
Inspried by a patch by Takeshi Kihara in the BSP.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add ID and Kconfig entry for the Renesas R8A77990 E3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Here we do a couple of minor fixes like:
- Move .ivt section to the very beginning of the image
by default which allows us to use that image put right
at reset vector (usually 0x0)
- Improve relocation fix-up which became required once
we moved .ivt and understood a problem with existing implementation
where we relied on a particular placement of sections.
Now we don't care about placement because we just explicitly
check for .text and in case of ARCompact .ivt sections
- Re-implemnt do_reset() such that it calls reset_cpu() which
could implmented for a particular board
And hte most important part we introduce support for yet another
devboard from Synopsys - EMDK.
Synopsys DesignWare ARC EM Development Kit (ARC EMDK) is
an FPGA-based development platform from Synopsys aimed to speed-up
development of software for ARC EM cores and entire subsystems based on
ARC EM like Data Fusion, Secure and Sensor & Control subsystems.
U-Boot is supposed to be used as a primary bootloader on EMDK allowing
users to easily load and start their application from micro-SD card.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This will allow for board-specific implementation of reset.
Default version will just stop execution with help of BRK instruction.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
For quite some time we have a GCC's built-in which inserts BRK
instruction so let's use it instead of simple insertion of in-line
assembly.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This is useful for cases when U-Boot image is put in ROM and
reset vector points to 0 where the very beginnign of the image reside.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We used to have the one and only linker script for all ARC boards
and so we relied on a particular order of symbols there.
Because of that we used __ivt_end as the marker of the end of all the
code which won't be true any longer if we move .ivt section to any other
place. That said we'd better check for each section separately.
A couple of other improvements:
1. There's no point to include the marker of section end in interested
range because its address is beyond the section, i.e. we should
compare with "<" but not "<=".
2. .ivt section for ARCv2 cores is just an array of 32-bit ints and
they are not swapped even on little-endia cores while in case of
ARCompact cores .ivt contains valid code so swapping is required.
3. Just in case add check for ARC600 which is also ARCompact
and its .ivt is normal code.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
