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x86: irq: Parse number of PIRQ links from device tree

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The "intel,pirq-link" property in Intel IRQ router's dt bindings
has two cells, where the second one represents the number of PIRQ
links on the platform. However current driver does not parse this
information from device tree. This adds the codes to do the parse
and save it for future use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2018-06-12 01:26:45 -07:00
parent 558f3ed9c8
commit dcec5d565a
2 changed files with 12 additions and 4 deletions
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14
arch/x86/cpu/irq.c
View File

@ -116,10 +116,16 @@ static int create_pirq_routing_table(struct udevice *dev)
return -EINVAL;
}
ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
if (ret == -1)
return ret;
priv->link_base = ret;
cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
if (!cell || len != 8)
return -EINVAL;
priv->link_base = fdt_addr_to_cpu(cell[0]);
priv->link_num = fdt_addr_to_cpu(cell[1]);
if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
debug("Limiting supported PIRQ link number from %d to %d\n",
priv->link_num, CONFIG_MAX_PIRQ_LINKS);
priv->link_num = CONFIG_MAX_PIRQ_LINKS;
}
priv->irq_mask = fdtdec_get_int(blob, node,
"intel,pirq-mask", PIRQ_BITMAP);

2
arch/x86/include/asm/irq.h
View File

@ -29,6 +29,7 @@ enum pirq_config {
*
* @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
* @link_base: link value base number
* @link_num: number of PIRQ links supported
* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
@ -39,6 +40,7 @@ enum pirq_config {
struct irq_router {
int config;
u32 link_base;
int link_num;
u16 irq_mask;
u32 bdf;
u32 ibase;