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x86: irq: Remove chipset specific irq router drivers

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At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use
the common one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2018-06-03 19:04:22 -07:00
parent 0a6fb5b577
commit bc728b1bc0
10 changed files with 70 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/x86/cpu/irq.c
View File

@ -237,7 +237,7 @@ static void irq_enable_sci(struct udevice *dev)
}
}
int irq_router_common_init(struct udevice *dev)
int irq_router_probe(struct udevice *dev)
{
int ret;
@ -256,11 +256,6 @@ int irq_router_common_init(struct udevice *dev)
return 0;
}
int irq_router_probe(struct udevice *dev)
{
return irq_router_common_init(dev);
}
ulong write_pirq_routing_table(ulong addr)
{
if (!gd->arch.pirq_routing_table)

2
arch/x86/cpu/quark/Makefile
View File

@ -2,6 +2,6 @@
#
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += car.o dram.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o

48
arch/x86/cpu/quark/irq.c
View File

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2015 Google, Inc
*/
#include <common.h>
#include <dm.h>
#include <asm/irq.h>
#include <asm/arch/device.h>
#include <asm/arch/quark.h>
int quark_irq_router_probe(struct udevice *dev)
{
struct quark_rcba *rcba;
u32 base;
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct quark_rcba *)base;
/*
* Route Quark PCI device interrupt pin to PIRQ
*
* Route device#23's INTA/B/C/D to PIRQA/B/C/D
* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
*/
writew(PIRQC, &rcba->rmu_ir);
writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
&rcba->d23_ir);
writew(PIRQD, &rcba->core_ir);
writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
&rcba->d20d21_ir);
return irq_router_common_init(dev);
}
static const struct udevice_id quark_irq_router_ids[] = {
{ .compatible = "intel,quark-irq-router" },
{ }
};
U_BOOT_DRIVER(quark_irq_router_drv) = {
.name = "quark_intel_irq",
.id = UCLASS_IRQ,
.of_match = quark_irq_router_ids,
.probe = quark_irq_router_probe,
};

26
arch/x86/cpu/quark/quark.c
View File

@ -7,6 +7,7 @@
#include <mmc.h>
#include <asm/io.h>
#include <asm/ioapic.h>
#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
@ -313,12 +314,37 @@ static void quark_usb_init(void)
writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
}
static void quark_irq_init(void)
{
struct quark_rcba *rcba;
u32 base;
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct quark_rcba *)base;
/*
* Route Quark PCI device interrupt pin to PIRQ
*
* Route device#23's INTA/B/C/D to PIRQA/B/C/D
* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
*/
writew(PIRQC, &rcba->rmu_ir);
writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
&rcba->d23_ir);
writew(PIRQD, &rcba->core_ir);
writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
&rcba->d20d21_ir);
}
int arch_early_init_r(void)
{
quark_pcie_init();
quark_usb_init();
quark_irq_init();
return 0;
}

2
arch/x86/cpu/queensbay/Makefile
View File

@ -2,5 +2,5 @@
#
# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
obj-y += fsp_configs.o irq.o
obj-y += fsp_configs.o
obj-y += tnc.o

64
arch/x86/cpu/queensbay/irq.c
View File

@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2015 Google, Inc
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
int queensbay_irq_router_probe(struct udevice *dev)
{
struct tnc_rcba *rcba;
u32 base;
dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
return irq_router_common_init(dev);
}
static const struct udevice_id queensbay_irq_router_ids[] = {
{ .compatible = "intel,queensbay-irq-router" },
{ }
};
U_BOOT_DRIVER(queensbay_irq_router_drv) = {
.name = "queensbay_intel_irq",
.id = UCLASS_IRQ,
.of_match = queensbay_irq_router_ids,
.probe = queensbay_irq_router_probe,
};

39
arch/x86/cpu/queensbay/tnc.c
View File

@ -98,6 +98,43 @@ int arch_cpu_init(void)
return x86_cpu_init_f();
}
static void tnc_irq_init(void)
{
struct tnc_rcba *rcba;
u32 base;
pci_read_config32(TNC_LPC, LPC_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
}
int arch_early_init_r(void)
{
int ret = 0;
@ -106,5 +143,7 @@ int arch_early_init_r(void)
ret = disable_igd();
#endif
tnc_irq_init();
return ret;
}

2
arch/x86/dts/crownbay.dts
View File

@ -151,7 +151,7 @@
#size-cells = <1>;
irq-router {
compatible = "intel,queensbay-irq-router";
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;

2
arch/x86/dts/galileo.dts
View File

@ -97,7 +97,7 @@
#size-cells = <1>;
irq-router {
compatible = "intel,quark-irq-router";
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;

7
arch/x86/include/asm/irq.h
View File

@ -58,11 +58,4 @@ struct pirq_routing {
#define PIRQ_BITMAP 0xdef8
/**
* irq_router_common_init() - Perform common x86 interrupt init
*
* This creates the PIRQ routing table and routes the IRQs
*/
int irq_router_common_init(struct udevice *dev);
#endif /* _ARCH_IRQ_H_ */