DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
initialize baudrate, flags, data and serial initialization,
only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
This patch adds support for MMC/SD on DA850/OMAP-L138.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.
It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP
Signed-off-by: Steve Sakoman <steve@sakoman.com>
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
All the global flag defines are the same across all arches. So unify them
in one place, and add a simple way for arches to extend for their needs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
base address.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch adds the base address for I2C.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
bad_cache_range actually returned true if the range was OK, but it was used
according to its name, which resulted in all valid dcache range invalidate/flush
operations being dropped. Hence, most DMA transfers resulted in garbage data.
This patch renames this function according to what it does, and it fixes the
interpretation of its return value by other functions. The chosen naming is the
same as for ARM926EJ-S in order to be consistent.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>
Use the same name as defined in the datasheet.
DSP_CLK -> DISP_CLK
Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Create a weak-aliased arch_cpu_init, so that we can get rid of CONFIG_ARCH_CPU_INIT
and always call arch_cpu_init.
This way we do not need to define CONFIG_ARCH_CPU_INIT in every board file, since
arch_cpu_init() is supposed to handle common CPU level code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Recent compiler generates unaligned memory access in armv7 default.
But current U-Boot does not allow unaligned memory access, so it causes
data abort exception.
This patch add compile option "-mno-unaligned-access" if it is available.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Gary Thomas <gary@mlbassoc.com>
In currently, when __bss_start is equal to __bss_end__,
The bss loop will clear all the things in memory space.
But just only when __bss_end__ greater than __bss_start__,
we do the clear bss section operation.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <wd@denx.de>
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
* 'master' of git://git.denx.de/u-boot-arm:
tegra: define fdt_load/fdt_high variables
tegra: enable bootz command
tegra: usb: Fix device enumeration problem of USB1
tegra: trimslice: set up serial flash pinmux
tegra: add pin_mux_spi() board initialization function
tegra: add GMC/GMD funcmux entry for SFLASH
tegra: bootcmd: start USB only when needed
tegra: bootcmd enhancements
tegra: add enterrcm command
tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
Add env vars describing U-Boot target board
tegra: usb: fix wrong error check
tegra: add ULPI on USB2 funcmux entry
tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
tegra: Add Tamonten Evaluation Carrier support
tegra: Use SD write-protect GPIO on Tamonten
tegra: Implement gpio_early_init() on Tamonten
tegra: Allow boards to perform early GPIO setup
tegra: plutux: Add device tree support
tegra: medcom: Add device tree support
tegra: Rework Tamonten support
beagle: add eeprom expansion board info for bct brettl4
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-usb:
CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250
EXYNOS5: USB: Fix incorrect USB base addresses
EXYNOS: Add power Enable/Disable for USB-EHCI
USB: EXYNOS: Set USB 2.0 HOST Link mode
EXYNOS5: Add structure for PMU registers
EXYNOS5: Fix system register structure
USB: EXYNOS: Incorporate EHCI review comments
Signed-off-by: Wolfgang Denk <wd@denx.de>
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra's boot ROM supports a mode whereby code may be downloaded and flash
programmed over a USB connection. On dev boards, this is typically entered
by holding down a "force recovery" button and resetting the CPU. However,
not all boards have such a button (one example is the Compulab Trimslice),
so a method to enter RCM from software is useful.
This change implements the command "enterrcm" to do this, and enables it
for all Tegra boards by default. Even on boards other than Trimslice,
controlling this over a UART may be useful, e.g. to allow simple remote
control without the need for mechanical button actuators, or hooking up
relays/... to the button.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
loop_count runs down from 10000, so the correct condition to error out
is ==0.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren.nvidia@gmail.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is needed as a prerequisite for Tegra USB ULPI support
within U-Boot.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch corrects the base addresses for USB_PHY and USB_OTG.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This patch corrects the SYSREG structure.
We have removed the sysreg.h added in the previous patchset
version as the sysreg structure is already defined in system.h.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This reverts commit fa042186b9.
It causes build warnings like this:
cpu.c:48:1: warning: -fstack-usage not supported for this target
[enabled by default]
Signed-off-by: Wolfgang Denk <wd@denx.de>
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
int cleanup_before_linux(void)
{
...
...
dcache_disable();
v7_outer_cache_disable();
invalidate_dcache_all();
}
1) invalidate_dcache_all call expects that all the caches has been
flushed, invalidated and there are no dirty entries prior to its
execution. In the above sequence dcache_disable() flushes, invalidates
the caches and turns off the mmu. But after it cleanups the cache
and before the mmu is disabled there is a cp_delay() function which
has STR instruction. On certain cores like the cortex-a15, cache hit
and a write can happen to a cache line even when the dcache is
disabled. So the above mentioned STR instruction creates a dirty entry
after cleaning. The mmu gets disabled after this.
2) invalidate_dcache_all invalidates the cache lines. Again on
cores like cortex-a15, invalidate instruction flushes the dirty
line as well. So some times the dirty line from sequence 1
can corrupt the memory resulting in a crash.
Fixing this by moving the get_cr() and cp_delay() calls before
cleaning up the cache, thus avoiding the dirty entry.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Introduce arch_early_init_r() function, which can be useful for doing
early initialization after relocation has happened.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
No need to define CONFIG_ARCH_CPU_INIT.
All mx28 based boards should use arch_cpu_init().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
This patch adds SPL support for SPEAr600. Currently only SNOR
(Serial NOR) flash support is included. Other boot devices
(NAND, MMC, USB ...) may be added with later patches.
Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
raise() likes to call printf() if it is available, but in SPL builds it
either is not available, or adds a large chunk to the resulting image
size.
So don't call it even if it is available.
This change reduces SPL size from 10KB to 6.3KB on hawkboard, for
example, using generic relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
In SPEAr configuration files, unnecessary paranthesis are used in some
\#defines. Remove them as they serve no purpose
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Earlier, architecture specific init code was mixed with board initialization
code in board/spear/... This patch updates architecture support for SPEAr in
latest u-boot and prints the SoC information.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The
driver for this device is already supported by u-boot, so configuring
board configuration file and defining base addresses etc to make use
of the common driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Xloader table was used primarily to inform u-boot about the DDR size. However,
now the ddr size is calculated at runtime which eliminates any need for the
Xloader table. So removing this unnecessary code.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SMI is the serial memory interface controller provided by ST.
Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
USB clocks will be required for fastboot, tftp
related functionalities. Move these clocks to
essential group inorder to have the functionality
working when non-essential clocks are not enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
GPMC clocks are currently getting enabled as a part
non-essential clocks. This will be required during
NOR boot. Move this to essential group to keep the
functionality, when non-essential clocks are not
enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
This reduced M,N couple corresponds to the advised value from
TI HW team.
Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.
Signed-off-by: Sebastien Jan <s-jan@ti.com>
The PLL setup values currently assume a 24 Mhz input clock.
This patch uses V_OSCK from the board config file to support boards
with different input clock rates.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so
Micron memory will not be detected!
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Some rams (Micron for example) return duplicate mr data on all byte lanes.
Users of the get_mr function currently don't deal with this duplicated
data gracefully. This patch detects the duplicated data and returns only
the expected 8 bit mr data.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Errata ID:i727
Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.
Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.
This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.
This will be used to skip the module configurations
that are retained across a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.
Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.
A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).
Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
The macro mistakenly referred to 32bit struct instead of 8bit one.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.
Fix the mask for these bits.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Previously, only the low 5 bits (NCH) were being transfered
from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed.
VTP_RECAL should be bit 15, not 18.
The only mainline board affected by this change is davinci_sonata.
The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT.
However, if the program that loads u-boot on these boards
copied the code from u-boot, they will need fixed as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Please get tested by acks before applying, where tested by
means an overnight memory test.
Thanks
Troy
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.
So always ensure that the size of memory used for testing is
aligned to the power of 2.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.
This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.
Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.
So take care of the above scenarios while calculating the
size of the actual ram.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
