brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-07 03:36:16 +09:00
Code Issues Projects Releases Wiki Activity

arm: Tegra: Use ODMDATA from BCT in IRAM

Browse Source 
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
This commit is contained in:
Tom Warren 2012-05-30 14:06:09 -07:00 committed by Albert ARIBAUD
parent f9f2f12e2c
commit 76e350b7a3
10 changed files with 25 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm/cpu/armv7/tegra2/ap20.c
View File

@ -314,9 +314,28 @@ void enable_scu(void)
writel(reg, &scu->scu_ctrl);
}
static u32 get_odmdata(void)
{
/*
* ODMDATA is stored in the BCT in IRAM by the BootROM.
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
* on T20 and T30 BCTs, which are locked down. If this changes
* in new chips (T114, etc.), we can revisit this algorithm.
*/
u32 bct_start, odmdata;
bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
}
void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 odmdata;
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@ -324,7 +343,8 @@ void init_pmc_scratch(void)
writel(0, &pmc->pmc_scratch1+i);
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
odmdata = get_odmdata();
writel(odmdata, &pmc->pmc_scratch20);
#ifdef CONFIG_TEGRA2_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */

4
arch/arm/include/asm/arch-tegra2/tegra2.h
View File

@ -60,6 +60,10 @@ struct timerus {
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
#define AP20_WB_RUN_ADDRESS 0x40020000
#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
/* These are the available SKUs (product types) for Tegra */
enum {
SKU_ID_T20 = 0x8,

1
include/configs/harmony.h
View File

@ -48,7 +48,6 @@
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F

1
include/configs/medcom.h
View File

@ -31,7 +31,6 @@
/* High-level configuration options */
#define V_PROMPT "Tegra2 (Medcom) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI

1
include/configs/paz00.h
View File

@ -35,7 +35,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */
#define CONFIG_BOARD_EARLY_INIT_F

1
include/configs/plutux.h
View File

@ -31,7 +31,6 @@
/* High-level configuration options */
#define V_PROMPT "Tegra2 (Plutux) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI

1
include/configs/seaboard.h
View File

@ -53,7 +53,6 @@
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F

1
include/configs/trimslice.h
View File

@ -43,7 +43,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
#define CONFIG_SYS_BOARD_ODMDATA 0x300c0011 /* lp?, 1GB, UARTA */
#define CONFIG_BOARD_EARLY_INIT_F

1
include/configs/ventana.h
View File

@ -42,7 +42,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F

1
include/configs/whistler.h
View File

@ -43,7 +43,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
#define CONFIG_SYS_BOARD_ODMDATA 0x2B080105 /* lp?, 512MB, UARTA */
#define CONFIG_BOARD_EARLY_INIT_F