Cache the value of the reg-io-width property for the future use.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
New callback will give a necessary information to fill up ACPI SPCR table,
for example. Maybe used later for other purposes.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change ADR_SPACE_SYSTEM_IO to SERIAL_ADDRESS_SPACE_IO to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
In some cases it would be good to know the settings, such as parity,
of current serial console. One example might be an ACPI SPCR table
to generate using these parameters.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Don't disable regulator which are tagged as "regulator-always-on" in DT.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jack Mitchell <jack@embed.me.uk>
Tested-by: Jack Mitchell <jack@embed.me.uk>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Richard Röjfors <richard@puffinpack.se>
Tested-by: Richard Röjfors <richard@puffinpack.se>
Reviewed-by: Felix Brack <fb@ltec.ch>
Tested-by: Felix Brack <fb@ltec.ch>
This functions allow us to get and remap I/O addresses by name, which is useful when there are multiple reg addresses indexed by reg-names property.
This is needed in bmips dma/eth patch series, but can also be used on many
other drivers.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We should not have exported functions in a driver. The i8042_disable()
function is used to disable the keyboard. Provide a remove() method
instead, which is the standard way of disabling a device.
We could potentially add a method to flush input but that does not seem
necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there are no users of the 64-byte v2 context. The v1 context is
only 16 bytes long and currently an error is raised if too much data is
returned from the EC.
Update the code to limit the size to 16 bytes.
Signed-off-by: Simon Glass <sjg@chromium.org>
If U-Boot is started from SPL or TPL, then those earlier phases deal with
the reset cause. On real hardware this cause may be lost once it is read.
Emulate that behaviour in sandbox by reporting a warm reset when a
previous phase has run since start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
We cannot be sure that the interface name takes up the full length of the
space available to it. Use strcpy() instead of memcpy() in this case. This
corrects a valgrind warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
The macros used to set the direction of the GPIO pins are misused,
resulting in a wrong behavior when trying to read the GPIO input level
from U-Boot.
A better macro is also used when setting the output direction.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Drop BMP_ALIGN_CENTER define in lcd.c and video_bmp.c as it is
already defined by splash.h. Include splash.h in bmp code.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
According to SD Specifications Part 1 Physical Layer Simplified Specification
Version 6.00 August 29, 2018, section 4.3.10 (Switch Function Command) and
section 5.6 (SCR register), SD cards version 1.00 and 1.01 do not support the
SD CMD 6.
Currently, U-Boot will issue CMD 6 unconditionally in sd_set_card_speed()
while configuring the bus for selected frequency. This will make SD cards
version 1.00 and 1.01 time out and thus fail detection altogether.
Fix this by not sending CMD 6 on such cards. Tested on Matsushita Electric
Industrial Co., Ltd. Japan RP-SD008B / Victor 8MB SD card, CU-SD008, which
is correctly detected with this patch as:
Device: sd@ee160000
Manufacturer ID: 1
OEM: 5041
Name: S008B
Bus Speed: 25000000
Mode : SD Legacy
Rd Block Len: 512
SD version 1.0
High Capacity: No
Capacity: 6.5 MiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This reverts commit 6f57c34473 since it
does not seem to work at least on rk3399.
The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud
rate prescaler register is readable only when USR[0] is zero. Since this
bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather
drop this than making the ns16550 debug uart more platform specific.
Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com
This release is fully packed with lots of glorious improvements in UEFI
land again!
- Make PE images more standards compliant
- Improve sandbox support
- Improve correctness
- Fix RISC-V execution on virt model
- Honor board defined top of ram (fixes a few boards)
- Imply DM USB access when distro boot is available
- Code cleanups
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-12-03
This release is fully packed with lots of glorious improvements in UEFI
land again!
- Make PE images more standards compliant
- Improve sandbox support
- Improve correctness
- Fix RISC-V execution on virt model
- Honor board defined top of ram (fixes a few boards)
- Imply DM USB access when distro boot is available
- Code cleanups
At present line_length is always calculated in video_post_probe(). But
some hardware may use a different line length, e.g. with a 1366-wide
display.
Allow the driver to set this value if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
This patch adds a DM driver for the MPC8xx watchdog.
Basically, the watchdog is enabled by default from the start and
SYPCR register has to be writen once to set the timeout and/or
deactivate the watchdog. Once written, it cannot be written again.
It means that wdt_stop() can be called before wdt_start() to stop the
watchdog, but cannot be called if wdt_start() has been called.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
After this change the m41t62.c can be used with RTC subsystem (i.e. date
command) which uses device model (DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
This change facilitates the conversion of m41t62 RTC driver to device
model (DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch moves the RTC M41T62 config define to Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.
DTS files are synchronized from Linux 4.19.
Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Filter out HS400 support on SoCs where HS400 is not supported yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Reorder the tmio_sd_set_clk_rate() function such that it handles all
of the clock requiests correctly. Specifically, before this patch,
clock request with (mmc->clock == 0 && mmc->clk_disable) could leave
the clock enabled, as the function would exit on if (!mmc->clock)
condition on top and will not handle the mmc->clk_disable at all.
Rather than band-aid fixing just that particular problem, reorder
the entire function to make it easier to understand and verify that
all the cases are covered. The function has three sections now:
First, if mmc->clock != 0, we calculate divider for the SD block.
Second, if mmc->clock != 0 and SD block clock are enabled and
current divider is not equal to the new divider, then
stop the clock and update the divider.
Third, if mmc->clk_disable is set, disable the clock, otherwise
enable the clock. This happens independently of divider
update now.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a feature where it can automatically disable clock output
when the bus is not in use. While this is useful, it also interferes with
switching the bus to 1.8V and other background tasks of the SD/MMC cards,
which require clock to be enabled.
This patch respects the mmc->clk_disable and only disables the clock when
the MMC core requests it. Otherwise the clock are continuously generated
on the bus.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.
Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
renesas and socionext platforms
Add HS400 properties parsing support to mmc_of_parse().
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The USB storage driver does not compile when CONFIG_BLK is set,
but DM_USB is not set, as we're missing the DM device links for
CONFIG_BLK enabled code paths.
So far it looks like nobody fell into this trap, because no board
enabled CONFIG_BLK and CONFIG_USB_STORAGE while not enabling
CONFIG_DM_USB, but we should still reflect that dependency properly
in Kconfig so that implicit enabling of CONFIG_USB_STORAGE works.
Signed-off-by: Alexander Graf <agraf@suse.de>
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.
The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.
The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.
As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Variable 'days' must be defined as signed int. Otherwise the conversion
fails for some dates, e.g. 2004-08-25. Cf function rtc_time64_to_tm() in
the Linux kernel source.
Fixes: 992c1db455 "drivers: rtc: resolve year 2038 problem in rtc_to_tm"
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
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Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dm
Fix sound on sandbox
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.
The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).
Tested on RK3399-Q7 on Haikou base board.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The "Flamingo" carrier-board for the RK3399-Q7 has a RV3029 populated
and the application will use the off-module RV3029 RTC including the
battery backed SRAM.
To support this use case, this commit includes the following changes:
* updates the rv3029 driver to use DM
* implements the read8/write8 operations
This syncs the implementation with the Linux code (based on 4.17),
porting the trickle-charger support from there (with improvements to
avoid unnecessary EEPROM updates) and adheres to the Linux DTS
binding.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The MicroCrystal RV3029 driver didn't have a Kconfig entry and was not used
anywhere. Add it to Kconfig to make it selectable.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There was an incorrect check when looping and finding the first
fast enough frequency in the freq_rang table. The code did
actually return the first that was either exactly correct or
too slow.
Signed-off-by: Richard Röjfors <richard@puffinpack.se>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There was a copy and paste error where the data
enable setting was written to the version register.
Signed-off-by: Richard Röjfors <richard@puffinpack.se>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Currently the else part of ofnode_get_addr_index function
does not fetch addresses based on the index but rather just
returns the base address. Fix that.
Signed-off-by: Keerthy <j-keerthy@ti.com>
At present these functions are not accessible outside the TPM library, but
in some cases we need to call them. Export them in the header file and add
a define for the SHA1 digest size.
Also adjust tpm_open() to call tpm_close() first so that the TPM is in a
known state before opening (e.g. by a previous phase of U-Boot).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this value is hard-coded in the function that generates a
square wave. Since sample rates vary between different hardware, it makes
more sense to have this as a parameter.
Update the function and its users.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function currently outputs twice as much data as it should and
overwrites its buffer as a result. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some RTC chips have child drivers, e.g. to provide access to their
non-volatile RAM. Scan for these when binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sandbox i2c works using emulation drivers which are currently children of
the i2c device:
rtc_0: rtc@43 {
reg = <0x43>;
compatible = "sandbox-rtc";
emul {
compatible = "sandbox,i2c-rtc";
};
};
In this case the emulation device is attached to i2c bus on address 0x43
and provides the Real-Time-Clock (RTC) functionality.
However this is not ideal, since every device on an I2C bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.
A better approach seems to be to add a separate node on the bus, an
'emulation parent'. This can be given a bogus address (such as 0xff) and
hides all the emulators away. Then we can use a phandle to point from the
device to the correct emualtor, and only on sandbox. The code to find an
emulator does not interfere with normal i2c operation.
Add a new UCLASS_I2C_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. This will be used in a
follow-on patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add two functions which can find a child device by uclass or by name.
The first is useful with Multi-Function-Devices (MFDs) to find one of a
particular type. The second is useful when only the name is known.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function may be useful to code outside of the code driver-model
implementation. Export it and add a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is a newline missing from quite a few printf() strings in these pmic
files. Fix them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.
This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.
This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.
The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This patch adds a DDR3 driver for MT7629 SoC.
Signed-off-by: Wu Zou <wu.zou@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Many SoCs from MediaTek have a high-speed uart. This UART is compatible
with the ns16550 in legacy mode. It has extra registers for high-speed
mode which can reach a maximum baudrate at 921600.
However this UART will no longer be compatible if it's in high-speed mode.
Some BootROM of MediaTek's SoCs will change the UART into high-speed mode
and the U-Boot must use this driver to initialize the UART.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a driver for MT7623 clock blocks.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop non-dm code and migrate into DM_SPI.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[jagan: Move config menu in DM_SPI area]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Rename platform_data include file as spi_pl022.h from pl022_spi.h,
this is generic notation used for spi platdata include files.
Acked-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This patch can drop unnecessary include files in
pl022_spi driver.
Acked-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
pl022 spi driver support both OF_CONTROL and PLATDATA, this
patch is trying to simplify the code that differentiating
platdata vs of_control.
- Move OF_CONTROL code at one place
- Handle clock setup code directly in pl022_spi_ofdata_to_platdata
Acked-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This allows to disable the USB driver model in SPL because it checks
the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for
regular non-SPL builds.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Common USB code is built whenever USB is enabled (in non-SPL builds).
The USB uclass is built whenever (SPL_)DM_USB is enabled. Both need to
be independent from CMD_USB.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
This allows building the SPL without driver model for USB. Since
CONFIG_SPL_DM_USB is enabled if and only if CONFIG_DM_USB was enabled
before, this patch does not change the build behaviour.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This debug print was not designed to be active in non-debug mode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Meson pinctrl needs generic pinctrl, rather than depending on it
select it
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
At present these subsystems are only supported in U-Boot proper but it is
sometimes necessary to support them in SPL, or even TPL. Update the
Kconfig and Makefile to support this. Also adjust GPIO so that it can be
used in TPL if required.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for disabling subpage write support via
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE.
Currently the Linux Arasan driver does not support subpage writes and in
case of running UBI and accessing the same UBI volume from both U-Boot
and Linux it is required to have the same subpage write configuration
else the location of the UBI headers (EC + VID) will be misaligned
(subpage vs page) and incompatible. Hence the need for disabling
subpage write support in the U-Boot Arasan NAND driver.
Signed-off-by: Martin Lund <malu@gomspace.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds MT7629 qspi driver for accessing SPI NOR flash.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
This driver, ported from the Linux meson-spi-spifc driver, add support
for this controller on the Amlogic Meson GX SoCs in U-Boot.
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.
This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.
Add support for setting these delays.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
Comment in Linux driver says that clock needs to be doubled only
if we use DDR modes, moreover divider has to be set accordingly.
U-boot driver doesn't declare support for any DDR modes and doesn't
set internal clock divider in CLKCR, so it doubles clock
unconditionally when new mode is used.
Some cards can't handle that and as result SPL fails to load u-boot.
Fixes: de9b1771c3 ("mmc: sunxi: Support new mode")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled
Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
The initial layout for such NAND chips was the following:
+----------------------------------------------------------------------------+
| 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 32 (free OOB) | 30 (ECC) |
+----------------------------------------------------------------------------+
This layout has a weakness: reading empty pages trigger ECC errors
(this is expected), but the hardware ECC engine tries to correct the
data anyway and creates itself bitflips, hence bitflips are detected
in erased pages while actually there are none in the NAND chip.
Two solutions have been found at the same time. One was to enlarge the
free OOB area to 64 bytes, changing the layout to be:
+----------------------------------------------------------------------------+
| 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 64 (free OOB) | 30 (ECC) |
+----------------------------------------------------------------------------+
^^
The very big drawbacks of this solution are:
1/ It prevents booting from NAND.
2/ The current Linux driver (marvell_nand) does not have such problem
because it already re-reads possible empty pages in raw mode before
checking for bitflips. Using different layouts in U-Boot and Linux
would simply not work.
As this driver does support raw reads now and uses it to check for
empty pages, let's forget about this broken hack and return to the
initial layout with only 32 free OOB bytes.
Fixes: ac56a3b30c ("mtd: nand: pxa3xx: add support for 2KB 8-bit flash")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
This only applies on BCH path.
When an empty page is read, it triggers an uncorrectable error. While
this is expected, the ECC engine might produce itself bitflips in the
read data under certain layouts. To overcome this situation, always
re-read the entire page in raw mode and check for the whole page to be
empty.
Also report the right number of bitflips if there are any.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Raw read support is added by editing a few code sections:
->handle_data_pio() includes the ECC bytes that are not consumed
anymore by the ECC engine.
->prepare_set_command() is changed so that the ECC bytes are
requested as part of the data I/O length.
->drain_fifo() shall also avoid checking the R/B pin too often
when in raw mode.
->read_page_raw()/->read_oob_raw() are written from scratch.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present these functions return 0 on success. For some devices we want
to know how many bytes were transferred. It seems useful to adjust the API
to be more like the POSIX read() and write() functions.
Update these two methods, a test and all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
It is useful to be able to invert the colours in some cases so that the
text matches the background colour. Add a parameter to the function to
support this.
It is strange that function takes a private data structure from another
driver as an argument. It seems better to pass the device and have the
function internally work out how to find its required information.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not normally useful, so change the code to avoid writing out every
data package. This can be enabled with #define DEBUG.
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds new commands to the EC related to setting and clearing events
as well as controlling power-related settings.
Signed-off-by: Simon Glass <sjg@chromium.org>
The LPC driver expects its buffer to be word-aligned. Add the required
flag to the uclass driver to ensure this.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no advantage to using a u8 for function parameters. It forces
the compiler to mask values and can increase code size. Also the command
enum has been extended to 16 bits. Update the functions to use uint
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
When the device tree is missing a correct spi slave description below
the bus (compatible "spi-flash" or spi-max-frequency are missing),
the 'set_speed' callback can be called with 'speed' == 0 Hz.
At least with cadence qspi, this leads to a division by zero.
Prevent this by initializing speed to 100 kHz in this case (same
fallback value as is done in 'dm_spi_claim_bus') and issue a warning
to console.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With drivers that have prefix names that are quite long (like
'versatile_') it is useful to have a wider column for the driver's
name when dumping the device driver tree.
Also update the tests to take into account the wider output format.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As the PCIe specification recommend reading the Vendor ID register
to determine if a Function is present, read the Vendor ID of a
non-existent Function must not result in system error, so we'd better
make the first CFG read to Vendor ID instead of Header Type register
in the PCIe enumeration.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add two functions to ADC uclass's:
- adc_raw_to_uV() to ease ADC raw value conversion to microvolts
- adc_channel_mask() to get channels on consumer side
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds GPIO support for the Mediatek MT7621 SoC, tested on
MT7688 (Gardena smart-gateway). The driver is loosly based on the
Linux kernel version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed checkpatch.pl warnings: Prefer 'unsigned int' to bare use of 'unsigned']
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds watchdog support for the Mediatek MT7621 SoC. The driver
is loosly based on the Linux kernel version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed merge conflict in drivers/watchdog/Kconfig]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The terminal escape sequence ESC [ <x> ; <y> H is used to set the cursor
position. According to the ECMA 48 standard the upper left corner in the
escape sequences is [1, 1]. The video uclass uses [0, 0] as upper left
corner.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix compiler warning
drivers/misc/fs_loader.c:193:9: warning: format ‘%d’ expects
argument of type ‘int’, but argument 5 has type ‘size_t
{aka long unsigned int}’ [-Wformat=]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of two staged ofnode_to_offset followed by
device_get_global_by_of_offset approach, direcly use the
device_get_global_by_ofnode to fetch the device.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add possibility to update the serial parity used.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Change static array to const when it is useful to save memory
(move stm32f7_setup=0x18 from .data to .rodata section)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add get_pin_mux ops support to display the pin muxing
description of the sandbox_pins[]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds gpio get_function ops support.
This function reports the state of a gpio.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add get_pin_muxing() ops to obtain the pin muxing description
a given pin index.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_name ops to obtain a pin name given a
pin index of a specified pin-controller.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pins_count ops to obtain the number of pins
owns by a pin-controller.
On STM32 SoCs bindings, each pin-controller owns
several gpio banks. Each GPIO bank can own up to 16 pins.
To obtain the total pins count, walk through each sub-nodes
(ie GPIO banks) and sum each GPIO banks pins number. For that
in probe() we build a list with each GPIO device reference found.
This list will also be used with future get_pin_muxing and get_pin_name
ops to speed up and optimize walk through all GPIO banks.
As this code is common to all STM32 SoCs, this code is put
under SPL_BUILD compilation flag to avoid to increase SPL code size
for STM32F7 which is limited to 32Ko.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Similarly to uclass_first_device_err(), add uclass_next_device_err()
which returns an error if there are no next devices in that uclass.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add pinctrl_get_pin_name() and pinctrl_get_pins_count() methods
to obtain pin's name and pin's muxing given a pin reference.
This will be used by the new pinmux command.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_muxing() which allows to display the muxing
of a given pin belonging to a pin-controller.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Testing and analysis shows that at the moment LPC32xx NAND SLC driver
can not get PL080 DMA backbone support in SPL build, because SPL NAND
loaders operate with subpage (ECC step to be precisely) reads, and
this is not supported in the NAND SLC + DMA + hardware ECC calculation
bundle.
The change removes a cautious build time warning and explicitly
disables DMA flavour of the driver for SPL builds, to reduce the
amound of #ifdef sections the code blocks are minimally reorganized.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Build option CONFIG_SYS_MAX_NAND_CHIPS is used by NXP LPC32xx NAND MLC
driver only, as a preparation for potential removal or replacement of
the option the change predefines CONFIG_SYS_MAX_NAND_CHIPS to 1, same
value is used by the single user Work Microwave Work 92105 board, thus
it will be safe now to remove the option as a board specific one.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
The pca953x_gpio driver uses default value of polarity inversion
register. For some devices like PCA9557 and MAX7310, their polarity
inversion register default value is 0xf0. So for high 4 ports, when
reading their values, the values are inverted as the actual level.
This patch clears the polarity inversion register to 0 at init, so
that the port read and write values are aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The earlier commit f4fcba5c5b ("clk: implement clk_set_defaults()")
which introduced the functionality for setting clock defaults such as
rates and parents will skip the processing when executing in a re-reloc
state. This for example can prevent the assigning of clock parents
when running in SPL code. Go ahead and remove this limitation.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Convert the Watchdog driver for AT91SAM9x processors to support
the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG"
to new "CONFIG_WDT_AT91" Kconfig option.
Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If _debug_uart_putc() is called before _debug_uart_init(), the
ns16550 debug uart driver hangs in a tight loop waiting for the
tx FIFO to get empty.
As this can happen via a printf sneaking in before the port calls
debug_uart_init(), let's rather ignore characters before the debug
uart is initialized.
This is done by reading the baudrate divisor and aborting if is zero.
Tested on socfpga_cyclone5_socrates.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use the uclass_foreach_dev() macro instead of the open coded version.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver provides support for Sandbox implementation of virtio
transport driver which is used for testing purpose only.
Two drivers are provided. The 2nd one is a driver that lacks the
'notify' op.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For v1.0 compliant device, it always assumes the member 'num_buffers'
exists in the struct virtio_net_hdr while the legacy driver only
presented 'num_buffers' when VIRTIO_NET_F_MRG_RXBUF was negotiated.
Without that feature the structure was 2 bytes shorter.
Update the driver to support the non-legacy device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By default QEMU creates legacy PCI transport devices, but we can
ask QEMU to create non-legacy one if we pass additional device
property/value pairs in the command line:
-device virtio-blk-pci,disable-legacy=true,disable-modern=false
This adds a new driver driver to support non-legacy (modern) device
mode. Previous driver/file name is changed accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add test cases to cover the two newly added PCI APIs:
dm_pci_find_next_capability() & dm_pci_find_next_ext_capability().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces two new APIs dm_pci_find_next_capability() and
dm_pci_find_next_ext_capability() to get PCI capability address
and PCI express extended capability address for a given PCI device
starting from a given offset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a transport driver that implements UCLASS_VIRTIO for
virtio over pci, which is commonly used on x86.
It only supports the legacy interface of the pci transport, which
is the default device that QEMU emulates.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds virtio block device driver support.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a new block interface type for VirtIO block devices.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
blk_next_free_devnum() can be helpful in some cases. Make it
a public API.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
part_init() is currently called in every DM BLK driver, either
in its bind() or probe() method. However we can use the BLK
uclass driver's post_probe() method to do it automatically.
Update all DM BLK drivers to adopt this change.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently the sandbox block driver uses priv_auto_alloc_size for
the driver data, however that's only available after the device
probe phase. In order to make it accessible in an earlier phase,
switch to use platdata_auto_alloc_size instead.
This patch is the prerequisite for the follow up patch of DM BLK
driver changes to work with Sandbox.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds virtio net device driver support.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
VirtIO can use various different buses and virtio devices are
commonly implemented as PCI devices. But virtual environments
without PCI support (a common situation in embedded devices
models) might use simple memory mapped device (“virtio-mmio”)
instead of the PCI device.
This adds a transport driver that implements UCLASS_VIRTIO for
virtio over mmio.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds support for managing virtual queue/ring, the channel
for high performance I/O between host and guest.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a new virtio uclass driver for “virtio” [1] family of
devices that are are found in virtual environments like QEMU,
yet by design they look like physical devices to the guest.
The uclass driver provides child_pre_probe() and child_post_probe()
methods to do some common operations for virtio device drivers like
device and driver supported feature negotiation, etc.
[1] http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some buses need to set up their child devices after they are probed.
Support a common child_post_probe() method for the uclass.
With this change, the two APIs uclass_pre_probe_device() and
uclass_post_probe_device() become symmetric.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for switching the endianness of regmap accesses via the
"little-endian", "big-endian", and "native-endian" boolean properties in
the device tree.
The default endianness is native endianness.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
It is useful to be able to treat the different ranges of a regmap
separately to be able to use distinct offset for them, but this is
currently not implemented in the regmap API.
To preserve backwards compatibility, add regmap_read_range and
regmap_write_range functions that take an additional parameter
'range_num' that identifies the range to operate on.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The regmap functions currently assume that all register map accesses
have a data width of 32 bits, but there are maps that have different
widths.
To rectify this, implement the regmap_raw_read and regmap_raw_write
functions from the Linux kernel API that specify the width of a desired
read or write operation on a regmap.
Implement the regmap_read and regmap_write functions using these raw
functions in a backwards-compatible manner.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add some debug output in cases where the initialization of a regmap
fails.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Both fdtdec_get_addr_size_fixed and of_address_to_resource can fail with
an error, which is not currently checked during regmap initialization.
Since the indentation depth is already quite deep, extract a new
'init_range' method to do the initialization.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
A newly created property is currently not freed if a name could not be
allocated. This patch fixes the resulting memory leak in the error
patch.
Reported-by: Coverity (CID: 184085)
Fixes: e369e58df7 ("core: Add functions to set properties in live-tree")
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which
supports initialization of the FPGA, as well as information gathering.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
This patch adds a driver for the bus associated with a IHS FPGA.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Makefile entries should be sorted.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
ofnode_read_simple_addr_cells may fail and return a negative error code.
Check for this when initializing regmaps.
Also check if both_len is zero, since this is perfectly possible, and
would lead to a division-by-zero further down the line.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Document the regmap_alloc() function.
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Commit f2006808f099: ("dm: core: parse chosen node") added a logic
to parse the chosen node during dm_scan_fdt_node(), but unfortunately
it missed adding the same logic in dm_scan_fdt_live(). This mirrors
the logic in the livetree version.
The weird thing is that commit f2006808f0 did update the test case
to test such logic, but even if I reset to that commit, the test case
still fails, and I have no idea how it could pass.
With this fix, the following 2 test cases now pass:
Test: dm_test_bus_children: bus.c
test/dm/bus.c:112, dm_test_bus_children(): num_devices ==
list_count_items(&uc->dev_head): Expected 7, got 6
Test: dm_test_fdt: test-fdt.c
test/dm/test-fdt.c:184, dm_test_fdt(): num_devices ==
list_count_items(&uc->dev_head): Expected 7, got 6
Fixes: f2006808f0 ("dm: core: parse chosen node")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently the comments of several APIs (eg: dm_init_and_scan()) say:
@pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
flag. If false bind all drivers.
The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt
documents the same that both device tree properties and driver flag
are supported.
However the implementation only checks these special device tree
properties without checking the driver flag at all. This updates
lists_bind_fdt() to consider both scenarios.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in http://patchwork.ozlabs.org/patch/996473/ :
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds a new API dm_ofnode_pre_reloc(), a livetree equivalent
API of dm_fdt_pre_reloc().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The description string should not contain unnecessary characters,
like the ending '\n' or the leading 'CPU:'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit fb01e07a95 accidentally broke initialisation of GPIO
descriptor flags from device tree: currently the active low
flag from gpio-specifier is always ignored. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.
Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Both GPIOs are optional, so we shouldn't fail if any is missing.
Without this fix reset is not deasserted if sleep GPIO is missing.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.
Fixes eMMC instability on Pinebook
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Commit 9c5b00973b ("Convert CONFIG_MTD_PARTITIONS et al to Kconfig")
introduced a publicly visible Kconfig entry for the
CONFIG_MTD_PARTITIONS option, while the rework on MTD partitioning
was in progress, and we somehow did not notice that the same Kconfig
entry was added by commit 4048a5c519 ("mtd: declare MTD_PARTITIONS
symbol in Kconfig"), but this time as an invisible entry (this can
only be selected by other options).
Keep the non-visible version of this symbol, since MTD_PARTITIONS is
not something the user should be able to enable/disable directly.
Fixes: 4048a5c519 ("mtd: declare MTD_PARTITIONS symbol in Kconfig")
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
dfu_fill_entity_nand() uses find_dev_and_part() and mtdparts_init()
which are provided by cmd/mtdparts.c.
Add the dependency to avoid build failures when CMD_MTDPARTS is not
selected.
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Fixes: 6828e602b7 ("dfu: Migrate to Kconfig")
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
U-boot provides a mean to define default values for mtdids and mtdparts
when they're not defined in the environment. Patch mtd_probe_devices()
to use those default values when env_get("mtdparts") or
env_get("mtdids") return NULL.
This implementation is based on the logic found in cmd/mtdparts.c.
Fixes: 5db66b3aee ("cmd: mtd: add 'mtd' command")
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds check for command response CRC failure. The driver
is currently ignoring CRC check failure on command resposes which
have CRC atteched to it, which can be potentially dangerous. Even
more grueling problem happens when the command response is followed
by data transfer though, as in that case, the dwmci_data_transfer()
function will spin until it reaches the 240s timeout.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The commit
484fdf5ba0 ("dm: Add support for all targets which requires MANUAL_RELOC")
introduces subtle typo, i.e. missed semicolon.
Fixes: 484fdf5ba0 ("dm: Add support for all targets which requires MANUAL_RELOC")
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Update TI Keystone 2 driver to re-use common mdio lib.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Update TI CPSW driver to re-use common mdio lib
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update to use SPDX license identifier.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.
This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.
The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.
This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.
The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.
This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.
The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.
Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:
https://github.com/MediaTek-Labs/linkit-smart-uboot.git
Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.
This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Make sure to clear HS400 configuration when resetting the SCC block.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.
This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.
Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig
does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When the "w1 bus" command is used with no bus master present
a data abort may occur.
This is because uclass_first_device() returns zero, but sets the output
struct udevice pointer to NULL in the no device found case.
Fix w1_get_bus() to account for this and return an error code
as is expected by the callers.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Data abort was occurring when using "w1 bus" with a DS24B33 present.
The abort occurred in the ds24xxx_probe() because the struct w1_device
pointer was NULL. This is because that structure is allocated by
the parent device uclass (by .per_child_platdata_auto_alloc_size)
and thus the correct accessor is dev_get_parent_platdata() not
dev_get_platdata()
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
The 'status' variable in 'socfpga_load()' for both gen5 and arria10
is of type 'unsigned long' while it is always used as 'int' only.
Change it to 'int'.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.
- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Workaround makes FS as default mode on all affected socs.
Add support to check erratum-A005275 validity for an soc. This info is
required to determine whether a given soc is affected by this erratum.
Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used
to enable workaround for the errata
Force FS mode as default by:
- making EPS as FS
- setting PFSC bit to disable HS chirping
This workaround can be disabled by mentioning "no_erratum_a005275" in
hwconfig string
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Complete in the drivers directory the work started with
commit 83d290c56f ("SPDX: Convert all of our single
license tags to Linux Kernel style").
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
