mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 07:30:26 +09:00
ARM: rockchip: rv1108: Sync clock with vendor tree
Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Otavio Salvador
Philipp Tomsich
parent
765246a18c
commit
5d2cb15c77
@ -43,6 +43,12 @@ struct sysreset_reg {
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unsigned int glb_srst_snd_value;
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};
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struct softreset_reg {
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void __iomem *base;
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unsigned int sf_reset_offset;
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unsigned int sf_reset_num;
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};
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/**
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* clk_get_divisor() - Calculate the required clock divisior
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*
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@ -11,7 +11,11 @@
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define GPLL_HZ (1188 * 1000000)
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#define ACLK_PERI_HZ (148500000)
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#define HCLK_PERI_HZ (148500000)
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#define PCLK_PERI_HZ (74250000)
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#define ACLK_BUS_HZ (148500000)
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struct rv1108_clk_priv {
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struct rv1108_cru *cru;
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@ -80,6 +84,11 @@ enum {
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WORK_MODE_NORMAL = 1,
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DSMPD_SHIFT = 3,
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DSMPD_MASK = 1 << DSMPD_SHIFT,
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INTEGER_MODE = 1,
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GLOBAL_POWER_DOWN_SHIFT = 0,
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GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT,
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GLOBAL_POWER_DOWN = 1,
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GLOBAL_POWER_UP = 0,
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/* CLKSEL0_CON */
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CORE_PLL_SEL_SHIFT = 8,
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@ -90,11 +99,77 @@ enum {
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CORE_CLK_DIV_SHIFT = 0,
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CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
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/* CLKSEL_CON1 */
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PCLK_DBG_DIV_CON_SHIFT = 4,
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PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT,
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ACLK_CORE_DIV_CON_SHIFT = 0,
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ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT,
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/* CLKSEL_CON2 */
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ACLK_BUS_PLL_SEL_SHIFT = 8,
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ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT,
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ACLK_BUS_PLL_SEL_GPLL = 0,
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ACLK_BUS_PLL_SEL_APLL = 1,
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ACLK_BUS_PLL_SEL_DPLL = 2,
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ACLK_BUS_DIV_CON_SHIFT = 0,
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ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
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ACLK_BUS_DIV_CON_WIDTH = 5,
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/* CLKSEL_CON3 */
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PCLK_BUS_DIV_CON_SHIFT = 8,
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PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT,
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HCLK_BUS_DIV_CON_SHIFT = 0,
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HCLK_BUS_DIV_CON_MASK = 0x1f,
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/* CLKSEL_CON4 */
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CLK_DDR_PLL_SEL_SHIFT = 8,
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CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT,
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CLK_DDR_DIV_CON_SHIFT = 0,
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CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT,
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/* CLKSEL_CON19 */
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CLK_I2C1_PLL_SEL_SHIFT = 15,
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CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT,
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CLK_I2C1_PLL_SEL_DPLL = 0,
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CLK_I2C1_PLL_SEL_GPLL = 1,
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CLK_I2C1_DIV_CON_SHIFT = 8,
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CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT,
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CLK_I2C0_PLL_SEL_SHIFT = 7,
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CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT,
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CLK_I2C0_DIV_CON_SHIFT = 0,
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CLK_I2C0_DIV_CON_MASK = 0x7f,
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I2C_DIV_CON_WIDTH = 7,
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/* CLKSEL_CON20 */
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CLK_I2C3_PLL_SEL_SHIFT = 15,
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CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT,
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CLK_I2C3_PLL_SEL_DPLL = 0,
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CLK_I2C3_PLL_SEL_GPLL = 1,
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CLK_I2C3_DIV_CON_SHIFT = 8,
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CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT,
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CLK_I2C2_PLL_SEL_SHIFT = 7,
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CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT,
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CLK_I2C2_DIV_CON_SHIFT = 0,
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CLK_I2C2_DIV_CON_MASK = 0x7f,
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/* CLKSEL_CON22 */
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CLK_SARADC_DIV_CON_SHIFT= 0,
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CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
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CLK_SARADC_DIV_CON_WIDTH= 10,
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/* CLKSEL_CON23 */
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ACLK_PERI_PLL_SEL_SHIFT = 15,
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ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT,
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ACLK_PERI_PLL_SEL_GPLL = 0,
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ACLK_PERI_PLL_SEL_DPLL = 1,
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PCLK_PERI_DIV_CON_SHIFT = 10,
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PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT,
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HCLK_PERI_DIV_CON_SHIFT = 5,
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HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT,
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ACLK_PERI_DIV_CON_SHIFT = 0,
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ACLK_PERI_DIV_CON_MASK = 0x1f,
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PERI_DIV_CON_WIDTH = 5,
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/* CLKSEL24_CON */
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MAC_PLL_SEL_SHIFT = 12,
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MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
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@ -105,6 +180,17 @@ enum {
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MAC_CLK_DIV_MASK = 0x1f,
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MAC_CLK_DIV_SHIFT = 0,
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/* CLKSEL25_CON */
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EMMC_PLL_SEL_SHIFT = 12,
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EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT,
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EMMC_PLL_SEL_DPLL = 0,
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EMMC_PLL_SEL_GPLL,
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EMMC_PLL_SEL_OSC,
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/* CLKSEL26_CON */
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EMMC_CLK_DIV_SHIFT = 8,
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EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT,
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/* CLKSEL27_CON */
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SFC_PLL_SEL_SHIFT = 7,
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
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@ -112,5 +198,61 @@ enum {
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SFC_PLL_SEL_GPLL = 1,
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SFC_CLK_DIV_SHIFT = 0,
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SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT,
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/* CLKSEL28_CON */
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ACLK_VIO1_PLL_SEL_SHIFT = 14,
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ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT,
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VIO_PLL_SEL_DPLL = 0,
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VIO_PLL_SEL_GPLL = 1,
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ACLK_VIO1_CLK_DIV_SHIFT = 8,
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ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH = 5,
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ACLK_VIO0_PLL_SEL_SHIFT = 6,
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ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT,
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ACLK_VIO0_CLK_DIV_SHIFT = 0,
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ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
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/* CLKSEL29_CON */
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PCLK_VIO_CLK_DIV_SHIFT = 8,
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PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
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HCLK_VIO_CLK_DIV_SHIFT = 0,
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HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
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/* CLKSEL32_CON */
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DCLK_VOP_SEL_SHIFT = 7,
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DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_HDMI = 0,
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DCLK_VOP_SEL_PLL = 1,
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DCLK_VOP_PLL_SEL_SHIFT = 6,
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DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT,
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DCLK_VOP_PLL_SEL_GPLL = 0,
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DCLK_VOP_PLL_SEL_DPLL = 1,
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DCLK_VOP_CLK_DIV_SHIFT = 0,
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DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
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DCLK_VOP_DIV_CON_WIDTH = 6,
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/* SOFTRST1_CON*/
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DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0,
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DDRPHY_SRSTN_CLKDIV_REQ = 1,
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DDRPHY_SRSTN_CLKDIV_DIS = 0,
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DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT,
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DDRPHY_SRSTN_REQ_SHIFT = 1,
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DDRPHY_SRSTN_REQ = 1,
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DDRPHY_SRSTN_DIS = 0,
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DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT,
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DDRPHY_PSRSTN_REQ_SHIFT = 2,
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DDRPHY_PSRSTN_REQ = 1,
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DDRPHY_PSRSTN_DIS = 0,
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DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT,
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/* SOFTRST2_CON*/
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DDRUPCTL_PSRSTN_REQ_SHIFT = 0,
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DDRUPCTL_PSRSTN_REQ = 1,
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DDRUPCTL_PSRSTN_DIS = 0,
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DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT,
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DDRUPCTL_NSRSTN_REQ_SHIFT = 1,
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DDRUPCTL_NSRSTN_REQ = 1,
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DDRUPCTL_NSRSTN_DIS = 0,
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DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT,
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};
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#endif
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@ -17,6 +17,8 @@
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#include <dm/lists.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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@ -35,6 +37,9 @@ enum {
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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/* use integer mode */
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static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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{
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@ -57,6 +62,58 @@ static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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return id;
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}
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static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rv1108_pll_id(clk_id);
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struct rv1108_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/*
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* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_SLOW << WORK_MODE_SHIFT);
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/* use integer mode */
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rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
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rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
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(div->postdiv1 << POSTDIV1_SHIFT |
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div->postdiv2 << POSTDIV2_SHIFT |
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div->refdiv << REFDIV_SHIFT));
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rk_clrsetreg(&pll->con2, FRACDIV_MASK,
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(div->refdiv << REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
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udelay(1);
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/*
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* set PLL into normal mode.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_NORMAL << WORK_MODE_SHIFT);
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return 0;
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}
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static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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enum rk_clk_id clk_id)
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{
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@ -74,7 +131,7 @@ static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
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postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
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postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
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refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
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refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
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freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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} else {
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freq = OSC_HZ;
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@ -154,6 +211,326 @@ static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
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return rv1108_saradc_get_clk(cru);
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}
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static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
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return rv1108_aclk_vio1_get_clk(cru);
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}
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static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
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/*HCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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HCLK_VIO_CLK_DIV_MASK,
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3 << HCLK_VIO_CLK_DIV_SHIFT);
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/*PCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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PCLK_VIO_CLK_DIV_MASK,
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3 << PCLK_VIO_CLK_DIV_SHIFT);
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return rv1108_aclk_vio0_get_clk(cru);
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}
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static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[32]);
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div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
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DCLK_VOP_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 64);
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rk_clrsetreg(&cru->clksel_con[32],
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DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
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DCLK_VOP_SEL_SHIFT,
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(src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
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(DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
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(DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
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return rv1108_dclk_vop_get_clk(cru);
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}
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|
||||
static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
val = readl(&cru->clksel_con[2]);
|
||||
div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
|
||||
ACLK_BUS_DIV_CON_WIDTH);
|
||||
|
||||
return DIV_TO_RATE(parent_rate, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
|
||||
{
|
||||
int src_clk_div;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
|
||||
assert(src_clk_div < 32);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[2],
|
||||
ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
|
||||
(src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
|
||||
(ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
|
||||
|
||||
return rv1108_aclk_bus_get_clk(cru);
|
||||
}
|
||||
|
||||
static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
val = readl(&cru->clksel_con[23]);
|
||||
div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
|
||||
PERI_DIV_CON_WIDTH);
|
||||
|
||||
return DIV_TO_RATE(parent_rate, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
val = readl(&cru->clksel_con[23]);
|
||||
div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
|
||||
PERI_DIV_CON_WIDTH);
|
||||
|
||||
return DIV_TO_RATE(parent_rate, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
|
||||
{
|
||||
u32 div, val;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
val = readl(&cru->clksel_con[23]);
|
||||
div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
|
||||
PERI_DIV_CON_WIDTH);
|
||||
|
||||
return DIV_TO_RATE(parent_rate, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
|
||||
{
|
||||
int src_clk_div;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
|
||||
assert(src_clk_div < 32);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[23],
|
||||
ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
|
||||
(src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
|
||||
(ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
|
||||
|
||||
return rv1108_aclk_peri_get_clk(cru);
|
||||
}
|
||||
|
||||
static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
|
||||
{
|
||||
int src_clk_div;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
|
||||
assert(src_clk_div < 32);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[23],
|
||||
HCLK_PERI_DIV_CON_MASK,
|
||||
(src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
|
||||
|
||||
return rv1108_hclk_peri_get_clk(cru);
|
||||
}
|
||||
|
||||
static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
|
||||
{
|
||||
int src_clk_div;
|
||||
ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
|
||||
assert(src_clk_div < 32);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[23],
|
||||
PCLK_PERI_DIV_CON_MASK,
|
||||
(src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
|
||||
|
||||
return rv1108_pclk_peri_get_clk(cru);
|
||||
}
|
||||
|
||||
static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
|
||||
{
|
||||
u32 div, con;
|
||||
|
||||
switch (clk_id) {
|
||||
case SCLK_I2C0_PMU:
|
||||
con = readl(&cru->clksel_con[19]);
|
||||
div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,
|
||||
I2C_DIV_CON_WIDTH);
|
||||
break;
|
||||
case SCLK_I2C1:
|
||||
con = readl(&cru->clksel_con[19]);
|
||||
div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,
|
||||
I2C_DIV_CON_WIDTH);
|
||||
break;
|
||||
case SCLK_I2C2:
|
||||
con = readl(&cru->clksel_con[20]);
|
||||
div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,
|
||||
I2C_DIV_CON_WIDTH);
|
||||
break;
|
||||
case SCLK_I2C3:
|
||||
con = readl(&cru->clksel_con[20]);
|
||||
div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,
|
||||
I2C_DIV_CON_WIDTH);
|
||||
break;
|
||||
default:
|
||||
printf("do not support this i2c bus\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return DIV_TO_RATE(GPLL_HZ, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz)
|
||||
{
|
||||
int src_clk_div;
|
||||
|
||||
/* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
|
||||
src_clk_div = GPLL_HZ / hz;
|
||||
assert(src_clk_div - 1 <= 127);
|
||||
|
||||
switch (clk_id) {
|
||||
case SCLK_I2C0_PMU:
|
||||
rk_clrsetreg(&cru->clksel_con[19],
|
||||
CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
|
||||
(src_clk_div << CLK_I2C0_DIV_CON_SHIFT) |
|
||||
(CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
|
||||
break;
|
||||
case SCLK_I2C1:
|
||||
rk_clrsetreg(&cru->clksel_con[19],
|
||||
CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
|
||||
(src_clk_div << CLK_I2C1_DIV_CON_SHIFT) |
|
||||
(CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
|
||||
break;
|
||||
case SCLK_I2C2:
|
||||
rk_clrsetreg(&cru->clksel_con[20],
|
||||
CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
|
||||
(src_clk_div << CLK_I2C2_DIV_CON_SHIFT) |
|
||||
(CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
|
||||
break;
|
||||
case SCLK_I2C3:
|
||||
rk_clrsetreg(&cru->clksel_con[20],
|
||||
CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
|
||||
(src_clk_div << CLK_I2C3_DIV_CON_SHIFT) |
|
||||
(CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
|
||||
break;
|
||||
default:
|
||||
printf("do not support this i2c bus\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rv1108_i2c_get_clk(cru, clk_id);
|
||||
}
|
||||
|
||||
static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru)
|
||||
{
|
||||
u32 div, con;
|
||||
ulong mmc_clk;
|
||||
|
||||
con = readl(&cru->clksel_con[26]);
|
||||
div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);
|
||||
|
||||
con = readl(&cru->clksel_con[25]);
|
||||
|
||||
if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC)
|
||||
mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;
|
||||
else
|
||||
mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;
|
||||
|
||||
debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);
|
||||
return mmc_clk;
|
||||
}
|
||||
|
||||
static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate)
|
||||
{
|
||||
int div;
|
||||
u32 pll_rate;
|
||||
|
||||
div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);
|
||||
|
||||
if (div < 127) {
|
||||
debug("%s source gpll\n", __func__);
|
||||
rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
|
||||
(EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT));
|
||||
pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
} else {
|
||||
debug("%s source 24m\n", __func__);
|
||||
rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
|
||||
(EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT));
|
||||
pll_rate = OSC_HZ;
|
||||
}
|
||||
|
||||
div = DIV_ROUND_UP(pll_rate / 2, rate);
|
||||
rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,
|
||||
((div - 1) << EMMC_CLK_DIV_SHIFT));
|
||||
|
||||
debug("%s set_rate %ld div %d\n", __func__, rate, div);
|
||||
|
||||
return DIV_TO_RATE(pll_rate, div);
|
||||
}
|
||||
|
||||
static ulong rv1108_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
@ -163,6 +540,29 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
|
||||
return rkclk_pll_get_rate(priv->cru, clk->id);
|
||||
case SCLK_SARADC:
|
||||
return rv1108_saradc_get_clk(priv->cru);
|
||||
case ACLK_VIO0:
|
||||
return rv1108_aclk_vio0_get_clk(priv->cru);
|
||||
case ACLK_VIO1:
|
||||
return rv1108_aclk_vio1_get_clk(priv->cru);
|
||||
case DCLK_VOP:
|
||||
return rv1108_dclk_vop_get_clk(priv->cru);
|
||||
case ACLK_PRE:
|
||||
return rv1108_aclk_bus_get_clk(priv->cru);
|
||||
case ACLK_PERI:
|
||||
return rv1108_aclk_peri_get_clk(priv->cru);
|
||||
case HCLK_PERI:
|
||||
return rv1108_hclk_peri_get_clk(priv->cru);
|
||||
case PCLK_PERI:
|
||||
return rv1108_pclk_peri_get_clk(priv->cru);
|
||||
case SCLK_I2C0_PMU:
|
||||
case SCLK_I2C1:
|
||||
case SCLK_I2C2:
|
||||
case SCLK_I2C3:
|
||||
return rv1108_i2c_get_clk(priv->cru, clk->id);
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
case SCLK_EMMC_SAMPLE:
|
||||
return rv1108_mmc_get_clk(priv->cru);
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
@ -183,6 +583,37 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
|
||||
case SCLK_SARADC:
|
||||
new_rate = rv1108_saradc_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case ACLK_VIO0:
|
||||
new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case ACLK_VIO1:
|
||||
new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case DCLK_VOP:
|
||||
new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case ACLK_PRE:
|
||||
new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case ACLK_PERI:
|
||||
new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case HCLK_PERI:
|
||||
new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case PCLK_PERI:
|
||||
new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case SCLK_I2C0_PMU:
|
||||
case SCLK_I2C1:
|
||||
case SCLK_I2C2:
|
||||
case SCLK_I2C3:
|
||||
new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate);
|
||||
break;
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
new_rate = rv1108_mmc_set_clk(priv->cru, rate);
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
@ -197,14 +628,34 @@ static const struct clk_ops rv1108_clk_ops = {
|
||||
|
||||
static void rkclk_init(struct rv1108_cru *cru)
|
||||
{
|
||||
unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
|
||||
unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
|
||||
unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
unsigned int apll, dpll, gpll;
|
||||
unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
|
||||
|
||||
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
|
||||
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
|
||||
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
|
||||
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
|
||||
rv1108_aclk_vio0_set_clk(cru, 297000000);
|
||||
rv1108_aclk_vio1_set_clk(cru, 297000000);
|
||||
|
||||
/* configure apll */
|
||||
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
|
||||
rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
|
||||
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
|
||||
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
|
||||
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
|
||||
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
|
||||
|
||||
apll = rkclk_pll_get_rate(cru, CLK_ARM);
|
||||
dpll = rkclk_pll_get_rate(cru, CLK_DDR);
|
||||
gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
|
||||
0 << MAC_CLK_DIV_SHIFT);
|
||||
|
||||
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
|
||||
printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
|
||||
aclk_bus, aclk_peri, hclk_peri, pclk_peri);
|
||||
}
|
||||
|
||||
static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
|
||||
@ -228,8 +679,9 @@ static int rv1108_clk_probe(struct udevice *dev)
|
||||
static int rv1108_clk_bind(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
struct udevice *sys_child;
|
||||
struct udevice *sys_child, *sf_child;
|
||||
struct sysreset_reg *priv;
|
||||
struct softreset_reg *sf_priv;
|
||||
|
||||
/* The reset driver does not have a device node, so bind it here */
|
||||
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
||||
@ -251,6 +703,17 @@ static int rv1108_clk_bind(struct udevice *dev)
|
||||
if (ret)
|
||||
debug("Warning: software reset driver bind faile\n");
|
||||
#endif
|
||||
ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
|
||||
dev_ofnode(dev), &sf_child);
|
||||
if (ret) {
|
||||
debug("Warning: No rockchip reset driver: ret=%d\n", ret);
|
||||
} else {
|
||||
sf_priv = malloc(sizeof(struct softreset_reg));
|
||||
sf_priv->sf_reset_offset = offsetof(struct rv1108_cru,
|
||||
softrst_con[0]);
|
||||
sf_priv->sf_reset_num = 13;
|
||||
sf_child->priv = sf_priv;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -265,8 +728,8 @@ U_BOOT_DRIVER(clk_rv1108) = {
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = rv1108_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
|
||||
.ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
|
||||
.ops = &rv1108_clk_ops,
|
||||
.bind = rv1108_clk_bind,
|
||||
.ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
|
||||
.probe = rv1108_clk_probe,
|
||||
};
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#define ARMCLK 3
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_MAC 64
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
@ -35,20 +34,77 @@
|
||||
#define SCLK_SDMMC_SAMPLE 84
|
||||
#define SCLK_SDIO_SAMPLE 85
|
||||
#define SCLK_EMMC_SAMPLE 86
|
||||
#define SCLK_MAC_RX 87
|
||||
#define SCLK_MAC_TX 88
|
||||
#define SCLK_MACREF 89
|
||||
#define SCLK_MACREF_OUT 90
|
||||
#define SCLK_SARADC 91
|
||||
#define SCLK_VENC_CORE 87
|
||||
#define SCLK_HEVC_CORE 88
|
||||
#define SCLK_HEVC_CABAC 89
|
||||
#define SCLK_PWM0_PMU 90
|
||||
#define SCLK_I2C0_PMU 91
|
||||
#define SCLK_WIFI 92
|
||||
#define SCLK_CIFOUT 93
|
||||
#define SCLK_MIPI_CSI_OUT 94
|
||||
#define SCLK_CIF0 95
|
||||
#define SCLK_CIF1 96
|
||||
#define SCLK_CIF2 97
|
||||
#define SCLK_CIF3 98
|
||||
#define SCLK_DSP 99
|
||||
#define SCLK_DSP_IOP 100
|
||||
#define SCLK_DSP_EPP 101
|
||||
#define SCLK_DSP_EDP 102
|
||||
#define SCLK_DSP_EDAP 103
|
||||
#define SCLK_CVBS_HOST 104
|
||||
#define SCLK_HDMI_SFR 105
|
||||
#define SCLK_HDMI_CEC 106
|
||||
#define SCLK_CRYPTO 107
|
||||
#define SCLK_SPI 108
|
||||
#define SCLK_SARADC 109
|
||||
#define SCLK_TSADC 110
|
||||
#define SCLK_MAC_PRE 111
|
||||
#define SCLK_MAC 112
|
||||
#define SCLK_MAC_RX 113
|
||||
#define SCLK_MAC_REF 114
|
||||
#define SCLK_MAC_REFOUT 115
|
||||
#define SCLK_DSP_PFM 116
|
||||
#define SCLK_RGA 117
|
||||
#define SCLK_I2C1 118
|
||||
#define SCLK_I2C2 119
|
||||
#define SCLK_I2C3 120
|
||||
#define SCLK_PWM 121
|
||||
#define SCLK_ISP 122
|
||||
#define SCLK_USBPHY 123
|
||||
#define SCLK_I2S0_SRC 124
|
||||
#define SCLK_I2S1_SRC 125
|
||||
#define SCLK_I2S2_SRC 126
|
||||
#define SCLK_UART0_SRC 127
|
||||
#define SCLK_UART1_SRC 128
|
||||
#define SCLK_UART2_SRC 129
|
||||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_MACREF 131
|
||||
#define SCLK_MACREF_OUT 132
|
||||
|
||||
#define DCLK_VOP_SRC 185
|
||||
#define DCLK_HDMIPHY 186
|
||||
#define DCLK_VOP 187
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 192
|
||||
#define ACLK_PRE 193
|
||||
#define ACLK_CORE 194
|
||||
#define ACLK_ENMCORE 195
|
||||
#define ACLK_GMAC 196
|
||||
|
||||
#define ACLK_RKVENC 196
|
||||
#define ACLK_RKVDEC 197
|
||||
#define ACLK_VPU 198
|
||||
#define ACLK_CIF0 199
|
||||
#define ACLK_VIO0 200
|
||||
#define ACLK_VIO1 201
|
||||
#define ACLK_VOP 202
|
||||
#define ACLK_IEP 203
|
||||
#define ACLK_RGA 204
|
||||
#define ACLK_ISP 205
|
||||
#define ACLK_CIF1 206
|
||||
#define ACLK_CIF2 207
|
||||
#define ACLK_CIF3 208
|
||||
#define ACLK_PERI 209
|
||||
#define ACLK_GMAC 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO1 256
|
||||
@ -67,12 +123,24 @@
|
||||
#define PCLK_PWM 269
|
||||
#define PCLK_TIMER 270
|
||||
#define PCLK_PERI 271
|
||||
#define PCLK_GMAC 272
|
||||
#define PCLK_SARADC 273
|
||||
#define PCLK_GPIO0_PMU 272
|
||||
#define PCLK_I2C0_PMU 273
|
||||
#define PCLK_PWM0_PMU 274
|
||||
#define PCLK_ISP 275
|
||||
#define PCLK_VIO 276
|
||||
#define PCLK_MIPI_DSI 277
|
||||
#define PCLK_HDMI_CTRL 278
|
||||
#define PCLK_SARADC 279
|
||||
#define PCLK_DSP_CFG 280
|
||||
#define PCLK_BUS 281
|
||||
#define PCLK_EFUSE0 282
|
||||
#define PCLK_EFUSE1 283
|
||||
#define PCLK_WDT 284
|
||||
#define PCLK_GMAC 285
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 320
|
||||
#define HCLK_I2S1_8CH 321
|
||||
#define HCLK_I2S1_2CH 321
|
||||
#define HCLK_I2S2_2CH 322
|
||||
#define HCLK_NANDC 323
|
||||
#define HCLK_SDMMC 324
|
||||
@ -80,20 +148,37 @@
|
||||
#define HCLK_EMMC 326
|
||||
#define HCLK_PERI 327
|
||||
#define HCLK_SFC 328
|
||||
#define HCLK_RKVENC 329
|
||||
#define HCLK_RKVDEC 330
|
||||
#define HCLK_CIF0 331
|
||||
#define HCLK_VIO 332
|
||||
#define HCLK_VOP 333
|
||||
#define HCLK_IEP 334
|
||||
#define HCLK_RGA 335
|
||||
#define HCLK_ISP 336
|
||||
#define HCLK_CRYPTO_MST 337
|
||||
#define HCLK_CRYPTO_SLV 338
|
||||
#define HCLK_HOST0 339
|
||||
#define HCLK_OTG 340
|
||||
#define HCLK_CIF1 341
|
||||
#define HCLK_CIF2 342
|
||||
#define HCLK_CIF3 343
|
||||
#define HCLK_BUS 344
|
||||
#define HCLK_VPU 345
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SFC + 1)
|
||||
#define CLK_NR_CLKS (HCLK_VPU + 1)
|
||||
|
||||
/* reset id */
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_AD 1
|
||||
#define SRST_L2_AD 2
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CORE_PO 4
|
||||
#define SRST_CORE 5
|
||||
#define SRST_L2 6
|
||||
#define SRST_L2 6
|
||||
#define SRST_CORE_DBG 8
|
||||
#define PRST_DBG 9
|
||||
#define RST_DAP 10
|
||||
#define RST_DAP 10
|
||||
#define PRST_DBG_NIU 11
|
||||
#define ARST_STRC_SYS_AD 15
|
||||
|
||||
@ -160,9 +245,9 @@
|
||||
#define HRST_SYSBUS 75
|
||||
#define PRST_USBGRF 76
|
||||
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define HRST_PERIPH 83
|
||||
#define HRST_SDMMC 84
|
||||
#define HRST_SDIO 85
|
||||
@ -180,7 +265,7 @@
|
||||
#define HRST_HOST0_AUX 96
|
||||
#define HRST_HOST0_ARB 97
|
||||
#define SRST_HOST0_EHCIPHY 98
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_USBPOR 100
|
||||
#define SRST_UTMI0 101
|
||||
#define SRST_UTMI1 102
|
||||
@ -227,21 +312,21 @@
|
||||
#define HRST_VPU_NIU 141
|
||||
#define ARST_VPU 142
|
||||
#define HRST_VPU 143
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC 146
|
||||
#define HRST_RKVDEC 147
|
||||
#define SRST_RKVDEC_CABAC 148
|
||||
#define SRST_RKVDEC_CORE 149
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC 152
|
||||
#define HRST_RKVENC 153
|
||||
#define SRST_RKVENC_CORE 154
|
||||
|
||||
#define SRST_DSP_CORE 156
|
||||
#define SRST_DSP_SYS 157
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_OECM 159
|
||||
#define PRST_DSP_IOP_NIU 160
|
||||
#define ARST_DSP_EPP_NIU 161
|
||||
@ -259,7 +344,7 @@
|
||||
#define SRST_PMU_I2C0 173
|
||||
#define PRST_PMU_I2C0 174
|
||||
#define PRST_PMU_GPIO0 175
|
||||
#define PRST_PMU_INTMEM 176
|
||||
#define PRST_PMU_INTMEM 176
|
||||
#define PRST_PMU_PWM0 177
|
||||
#define SRST_PMU_PWM0 178
|
||||
#define PRST_PMU_GRF 179
|
||||
|
||||
Loading…
Reference in New Issue
Block a user