Remove silicon prefix. Automotive grade devices are using xazu instead
of xczu prefix.
The patch "fpga: xilinx: Check for substring in device ID validation"
(sha1: f72132673a)
enables this functionality for zynq devices that only substrings are
checked.
Unfortunately there is no way how to detect device grade that's why
this change is reasonable.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add missing zynq_board_read_rom_ethaddr() prototype reported by sparse.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This is the same patch as was done earlier.
Please look at Linux patch:
"arm64: zynqmp: Use only earlycon bootargs instead of full one"
(sha1: f3609c8d4af28b9cc22ca49bf8e529b582ec188c)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove overfetch, ratectrl, include-sg and src-issue dma properties.
Driver is not using them and they are also not documented in the binding
doc.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup bootmode variable based on bootmode selection.
This is helping with setting up boot method.
Also setup sdbootdevice.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dont read boot mode register directly read it using
zynqmp_mmio_read().
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is enabling support for SPL QSPI boot.
First of all it is necessary to generate atf-spi.ub which is different
format than atf-uboot.ub (this can be made as legacy image too)
ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point
address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'`
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR
-e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin
atf-uboot.ub
./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR
-n "atf-for-qspi" -E -d bl31.bin atf-spi.ub
This patch is using this QSPI layout with offsets:
0 boot.bin
512k atf-ub
640k u-boot.bin
1280k u-boot.img
Which corresponding by writing these images(read from MMC)
mmcinfo
sf probe
load mmc 0 10000000 boot.bin
sf erase 0 +$filesize
sf write 10000000 0 $filesize
load mmc 0 10000000 atf-spi.ub
sf erase 0x80000 +$filesize
sf write 10000000 0x80000 $filesize
load mmc 0 10000000 u-boot.bin
sf erase 0xa0000 +$filesize
sf write 10000000 0xa0000 $filesize
load mmc 0 10000000 u-boot.img
sf erase 0x140000 +$filesize
sf write 10000000 0x140000 $filesize
For testing u-boot running in EL3 you can break atf-spi.ub like this:
sf probe
sf erase 0x80000 +4
Then u-boot.img is executed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This reference is needed for pinctrl driver where some signals can be
routed directly to platform management unit (PMU).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This was caused by: "fs/fat: Reduce stack usage"
(sha1:2460098cffacd18729262e3ed36656e6943783ed) which converted
fat code to use malloc. But simple malloc is not freeing space
that's why full malloc implementation is needed.
Malloc space is added to RAM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not perform reset when panic happens because in the next reset
panic happens again and logs are overflood by the same errors.
This can be enabled by default and reset can be performed via watchdog.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is fixing two issues:
1. Insufficient stack size for fat fs buffers
2. Insufficient space in malloc area
Tested on zc702 and zc706.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The old CodingStyle document has been converted to ReST and moved
elsewhere. Link to the web version of this document instead.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
These ifdefs are protecting #include statements for files that have
never existed. AFAICT this hardware.h has been copied from the kernel
and the ifdefs have never served a role in U-Boot, so delete them.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Some QEMUs have a problem with time setup that's why
sleep test is failing. Introduce env__sleep_accurate
boardenv variable to have an option to skip sleep test.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
- avoid disturbing 0MiB partition size (in fact < 1MiB)
- test overlap limit between part1 and part2
- test gpt write with data with modifier 'M' for MiB
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
For external data, FIT has a optional property "data-position" which
can set the external data to a fixed offset to FIT beginning.
Add the support for this property in SPL FIT.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tomas Melin <tomas.melin@vaisala.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: "tomas.melin@vaisala.com" <tomas.melin@vaisala.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: "Cooper Jr., Franklin" <fcooper@ti.com>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Rick Altherr <raltherr@google.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Falcon mode was already working with SD card. This enables the
unlocking of NAND to allow the NAND read & write. This also
expands the README file based on the am335x describing how to
setup Falcon mode.
Signed-off-by: Adam Ford <aford173@gmail.com>
The Micron Flash is locked by default. This will automaticlly
unlock so manually unlocking is unnecessary in U-Boot.
Signed-off-by: Adam Ford <aford173@gmail.com>
The SPL-OS partition is 0x20000, so let's make
CONFIG_CMD_SPL_WRITE_SIZE same size. This should allow for better
falcon mode operation.
Signed-off-by: Adam Ford <aford173@gmail.com>
This symbol enables some library code used by various SATA drivers,
so make this a non-user-visible symbol select'ed by the respective
drivers, and let moveconfig handle the rest.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Use 'imply' here liberally to avoid the combinatorial explosion of
defconfig changes in the PowerPC boards.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Use 'imply' here liberally to avoid the combinatorial explosion of
defconfig changes in the PowerPC boards.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
The last user of this driver went away in August 2015 in commit:
b6073fd211 ("arm: Remove mx51_efikamx, mx51_efikasb boards")
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
The last user of this driver went away in June 2017, in commit:
98f705c9ce ("powerpc: remove 4xx support")
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
This driver really is DM GPIO one and so we need to have a correct
dependency, because DM alone doesn't provide required for CMD_GPIO
call and we're seeing build failures like this:
---------------------->8---------------------
cmd/built-in.o: In function 'do_gpio':
.../cmd/gpio.c:188: undefined reference to 'gpio_request'
...
---------------------->8---------------------
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is tedious to define both mask and bit-shift. <linux/bitfield.h>
provides a convenient way to get access to register fields with a
single shifted mask.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use DIV_ROUND_CLOSEST(). To make the JK value even more precise,
I used a bigger coefficient, then divide it by 512.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 682e09ff9f ("ARM: uniphier: add PLL init code for LD20 SoC")
missed to write the computed value to the SSCPLLCTRL2 register.
Fixes: 682e09ff9f ("ARM: uniphier: add PLL init code for LD20 SoC")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
denali.c has no driver entry in itself. It makes sense only when
compiled together with denali_dt.c
Let NAND_DENALI_DT select NAND_DENALI, and hide NAND_DENALI from
the Kconfig menu.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fix the link error for the combination of
CONFIG_ARCH_UNIPHIER_LD11=n
CONFIG_ARCH_UNIPHIER_LD20=n
CONFIG_ARCH_UNIPHIER_PXS3=y
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.
Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
dcache_exists, icache_exists, slc_exists and ioc_exists global
variables in "arch/arc/lib/cache.c" remain uninitialized if
SoC doesn't have corresponding HW.
This happens because we use the next constructions for their
definition and initialization:
-------------------------->>---------------------
int ioc_exists __section(".data");
if (/* condition */)
ioc_exists = 1;
-------------------------->>---------------------
That's quite a non-trivial issue as one may think of it.
The point is we intentionally put those variables in ".data" section
so they might survive relocation (remember we initilaize them very early
before relocation and continue to use after reloaction). While being
non-initialized and not explicitly put in .data section they would end-up
in ".bss" section which by definition is filled with zeroes.
But since we place those variables in .data section we need to care
about their proper initialization ourselves.
Also while at it we change their type to "bool" as more appropriate.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARCNUM [15:8] field in ARC_AUX_IDENTITY register allows us to
uniquely identify each core in a multi-core system.
I.e. with help of this macro each core may get its index in SMP system.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
DW SDIO controller has external CIU clock divider controlled via
register in the SDIO IP. Due to its unexpected default value
(we expected it to divide by 1 but in reality it divides by 8)
SDIO IP uses wrong CIU clock (it should be 100000000Hz but actual
is 12500000Hz) and works unstable (see STAR 9001204800).
So increase SDIO CIU frequency from actual 12500000Hz to 50000000Hz
by switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
