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ARM: uniphier: fix SSCPLL init code for LD11 SoC

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Commit 682e09ff9f ("ARM: uniphier: add PLL init code for LD20 SoC")
missed to write the computed value to the SSCPLLCTRL2 register.

Fixes: 682e09ff9f ("ARM: uniphier: add PLL init code for LD20 SoC")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Dai Okamura 2017-12-06 14:16:32 +09:00 committed by Masahiro Yamada
parent dc774e69bb
commit c30c44e799
1 changed files with 1 additions and 0 deletions
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arch/arm/mach-uniphier/clk/pll-base-ld20.c
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@ -48,6 +48,7 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
writel(tmp, base + 4);
udelay(50);
}