The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.
commit af778c6d9e
Author: Andrew Sharp <andywyse6@gmail.com>
Date: Wed Aug 1 12:27:16 2012 +0000
pci: fix errant data types and corresponding access functions
On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Several DIU registers were being initialized either unnecessarily or to
wrong values.
1) All interrupts were enabled even though there's no interrupt handler.
Interrupts were left enabled when booting Linux.
2) Don't configure a dummy area descriptor, since we don't support ADs
in U-Boot.
3) Don't configure any write-back buffer registers, since we don't use
that mode.
4) The default values for the THRESHOLDS, SYN_POL, and PLUT registers
should be used, so don't touch those registers either.
Signed-off-by: Timur Tabi <timur@freescale.com>
usb_hub_descriptor has to be packed as it's used for
communication with the device. Member wHubCharacteristics
violates the natural alignment rules.
Use explicit unaligned access functions for this member.
Fixes ARMv7 traping while using USB.
v2: fix typo found by Thomas Langer
v3: rebased on top of u-boot-usb/master
Signed-off-by: Lucas Stach <dev@lynxeye.de>
The "filesize" environment variable shall be read only when relevant
file is read.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Support for ext4 file system handling at DFU.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.
Tested with MCF5270 which have 4 chip selects.
Activate by #define CONFIG_CF_QSPI in board config.
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.
This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Merge mxc_setup_config1() into board_nand_init() in order to ease the addition
of i.MX5 support in the following patches.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC
errors left uncorrected after a call to this function.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use _mxc_nand_enable_hwecc() instead of duplicating its code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <computersforpeace@gmail.com>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND_CMD_ constants for lock/unlock should be in the header
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[scottwood@freescale.com: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <scottwood@freescale.com>
With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
This is commit 637957551c0ac80de8dfc7650d320c5a98c2c0c0 from Linux
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
[scottwood@freescale.com: picked from Linux into U-Boot]
Reported-by: Rafael Beims <rafael.beims@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Warning is:
xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'
Signed-off-by: Stephan Linz <linz@li-pro.net>
CC: Michal Simek <monstr@monstr.eu>
Initialize all possible uartlites and return the first
initialized port. For static configuration is initialization
done in userial_ports array.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Use CONFIG parameters only at one location to simplify
the code. Also create ace_readw/writew functions.
Signed-off-by: Michal Simek <monstr@monstr.eu>
With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.
Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
There were a couple of drivers that were actually using the flags
field of the cmd structure, despite the fact that no one ever
*set* that field. When we removed the field, those drivers failed
to compile. Replaced the references with the correct usage of
resp_type.
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.
The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:
mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000
The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.
It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.
On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Samsung SoC use the cmu control to set clock.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Useless code is removed, and get buswidth value.
buswidth value will be used to choice the 4bit or 8bit.
(Now used 4bit mode in sdhci.c by default)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Samsung SoC is broken busy waiting for R1b type.
And clk delay control value is modified the previosuly value.
(that value used at the s5p_mmc.c)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some boards have no Card Detect wired. In that case, set the CD test
bits in the standard interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When setting up the clocks in the sdhci driver, the "spec version"
must be masked off. Otherwise any time the vendor version is not 0,
the check will allways assume the interface is version 3. This breaks
when the interface is actually version 1 or 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
