mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-02 01:20:47 +09:00
Merge remote-tracking branch 'u-boot-imx/master'
This commit is contained in:
Albert ARIBAUD
commit
d193c1b6eb
8
Makefile
8
Makefile
@ -306,11 +306,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
|
||||
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
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||||
endif
|
||||
|
||||
ifeq ($(SOC),mx5)
|
||||
LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
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||||
endif
|
||||
ifeq ($(SOC),mx6)
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||||
LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
|
||||
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
|
||||
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
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||||
endif
|
||||
|
||||
ifeq ($(SOC),s5pc1xx)
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@ -776,6 +773,7 @@ clean:
|
||||
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
|
||||
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
|
||||
$(obj)tools/mk{smdk5250,}spl \
|
||||
$(obj)tools/mxsboot \
|
||||
$(obj)tools/ncb $(obj)tools/ubsha1
|
||||
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
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||||
$(obj)board/matrix_vision/*/bootscript.img \
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||||
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||||
@ -22,6 +22,7 @@
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||||
*/
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||||
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||||
#include <common.h>
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||||
#include <div64.h>
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||||
#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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||||
#include <asm/io.h>
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@ -30,16 +31,17 @@
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||||
static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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||||
u32 mfi = GET_PLL_MFI(reg);
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u32 mfn = GET_PLL_MFN(reg);
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||||
s32 mfn = GET_PLL_MFN(reg);
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||||
u32 mfd = GET_PLL_MFD(reg);
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u32 pd = GET_PLL_PD(reg);
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||||
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mfi = mfi <= 5 ? 5 : mfi;
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mfn = mfn >= 512 ? mfn - 1024 : mfn;
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mfd += 1;
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pd += 1;
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return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
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(mfd * pd)) << 10;
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return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
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||||
mfd * pd);
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}
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static u32 mx31_get_mpl_dpdgck_clk(void)
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@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
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u32 infreq;
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if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
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infreq = CONFIG_MX31_CLK32 * 1024;
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infreq = MXC_CLK32 * 1024;
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else
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infreq = CONFIG_MX31_HCLK_FREQ;
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infreq = MXC_HCLK;
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|
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return mx31_decode_pll(readl(CCM_MPCTL), infreq);
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}
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||||
@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <div64.h>
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#include <watchdog.h>
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||||
#include <asm/io.h>
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||||
@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR;
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, CONFIG_MX31_CLK32);
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do_div(tick, MXC_CLK32);
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return tick;
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}
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||||
static inline unsigned long long time_to_tick(unsigned long long time)
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||||
{
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time *= CONFIG_MX31_CLK32;
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||||
time *= MXC_CLK32;
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do_div(time, CONFIG_SYS_HZ);
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||||
return time;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
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||||
{
|
||||
us = us * CONFIG_MX31_CLK32 + 999999;
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||||
us = us * MXC_CLK32 + 999999;
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do_div(us, 1000000);
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||||
return us;
|
||||
}
|
||||
#else
|
||||
/* ~2% error */
|
||||
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
|
||||
/ CONFIG_SYS_HZ)
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||||
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
|
||||
#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
|
||||
#define US_PER_TICK (1000000 / MXC_CLK32)
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
@ -128,7 +128,7 @@ ulong get_timer_masked(void)
|
||||
{
|
||||
/*
|
||||
* get_ticks() returns a long long (64 bit), it wraps in
|
||||
* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
|
||||
* 5 * 10^6 days - long enough.
|
||||
*/
|
||||
@ -159,7 +159,7 @@ void __udelay(unsigned long usec)
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return CONFIG_MX31_CLK32;
|
||||
return MXC_CLK32;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0)
|
||||
static u32 decode_pll(u32 reg, u32 infreq)
|
||||
{
|
||||
u32 mfi = (reg >> 10) & 0xf;
|
||||
u32 mfn = reg & 0x3f;
|
||||
u32 mfd = (reg >> 16) & 0x3f;
|
||||
s32 mfn = reg & 0x3ff;
|
||||
u32 mfd = (reg >> 16) & 0x3ff;
|
||||
u32 pd = (reg >> 26) & 0xf;
|
||||
|
||||
mfi = mfi <= 5 ? 5 : mfi;
|
||||
mfn = mfn >= 512 ? mfn - 1024 : mfn;
|
||||
mfd += 1;
|
||||
pd += 1;
|
||||
|
||||
return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
|
||||
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
|
||||
mfd * pd);
|
||||
}
|
||||
|
||||
static u32 get_mcu_main_clk(void)
|
||||
@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void)
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
|
||||
fi *=
|
||||
decode_pll(readl(&ccm->mpctl),
|
||||
CONFIG_MX35_HCLK_FREQ);
|
||||
fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
|
||||
return fi / (arm_div * fd);
|
||||
}
|
||||
|
||||
@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void)
|
||||
u32 pdr4 = readl(&ccm->pdr4);
|
||||
u32 div;
|
||||
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
|
||||
div = (CCM_GET_DIVIDER(pdr4,
|
||||
MXC_CCM_PDR4_PER0_PRDF_MASK,
|
||||
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
|
||||
(CCM_GET_DIVIDER(pdr4,
|
||||
div = CCM_GET_DIVIDER(pdr4,
|
||||
MXC_CCM_PDR4_PER0_PODF_MASK,
|
||||
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
|
||||
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
|
||||
} else {
|
||||
div = CCM_GET_DIVIDER(pdr0,
|
||||
MXC_CCM_PDR0_PER_PODF_MASK,
|
||||
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
|
||||
freq /= get_ahb_div(pdr0);
|
||||
div *= get_ahb_div(pdr0);
|
||||
}
|
||||
return freq / div;
|
||||
}
|
||||
@ -193,25 +191,20 @@ u32 imx_get_uartclk(void)
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
u32 pdr4 = readl(&ccm->pdr4);
|
||||
|
||||
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
|
||||
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
|
||||
freq = get_mcu_main_clk();
|
||||
} else {
|
||||
freq = decode_pll(readl(&ccm->ppctl),
|
||||
CONFIG_MX35_HCLK_FREQ);
|
||||
}
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||||
freq /= ((CCM_GET_DIVIDER(pdr4,
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||||
MXC_CCM_PDR4_UART_PRDF_MASK,
|
||||
MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
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||||
(CCM_GET_DIVIDER(pdr4,
|
||||
else
|
||||
freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
|
||||
freq /= CCM_GET_DIVIDER(pdr4,
|
||||
MXC_CCM_PDR4_UART_PODF_MASK,
|
||||
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
|
||||
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
|
||||
return freq;
|
||||
}
|
||||
|
||||
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
|
||||
{
|
||||
u32 nfc_pdf, hsp_podf;
|
||||
u32 pll, ret_val = 0, usb_prdf, usb_podf;
|
||||
u32 pll, ret_val = 0, usb_podf;
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
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||||
ret_val = pll / (nfc_pdf + 1);
|
||||
break;
|
||||
case USB_CLK:
|
||||
usb_prdf = (reg4 >> 25) & 0x7;
|
||||
usb_podf = (reg4 >> 22) & 0x7;
|
||||
if (reg4 & 0x200) {
|
||||
usb_podf = (reg4 >> 22) & 0x3F;
|
||||
if (reg4 & 0x200)
|
||||
pll = get_mcu_main_clk();
|
||||
} else {
|
||||
pll = decode_pll(readl(&ccm->ppctl),
|
||||
CONFIG_MX35_HCLK_FREQ);
|
||||
}
|
||||
else
|
||||
pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
|
||||
|
||||
ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
|
||||
ret_val = pll / (usb_podf + 1);
|
||||
break;
|
||||
default:
|
||||
printf("Unknown clock: %d\n", clk);
|
||||
@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
|
||||
case UART2_BAUD:
|
||||
case UART3_BAUD:
|
||||
clk_sel = mpdr3 & (1 << 14);
|
||||
pre_pdf = (mpdr4 >> 13) & 0x7;
|
||||
pdf = (mpdr4 >> 10) & 0x7;
|
||||
pdf = (mpdr4 >> 10) & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
|
||||
break;
|
||||
case SSI1_BAUD:
|
||||
pre_pdf = (mpdr2 >> 24) & 0x7;
|
||||
pdf = mpdr2 & 0x3F;
|
||||
clk_sel = mpdr2 & (1 << 6);
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
case SSI2_BAUD:
|
||||
@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
|
||||
pdf = (mpdr2 >> 8) & 0x3F;
|
||||
clk_sel = mpdr2 & (1 << 6);
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
case CSI_BAUD:
|
||||
clk_sel = mpdr2 & (1 << 7);
|
||||
pre_pdf = (mpdr2 >> 16) & 0x7;
|
||||
pdf = (mpdr2 >> 19) & 0x7;
|
||||
pdf = (mpdr2 >> 16) & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
|
||||
break;
|
||||
case MSHC_CLK:
|
||||
pre_pdf = readl(&ccm->pdr1);
|
||||
@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
|
||||
pdf = (pre_pdf >> 22) & 0x3F;
|
||||
pre_pdf = (pre_pdf >> 28) & 0x7;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
case ESDHC1_CLK:
|
||||
clk_sel = mpdr3 & 0x40;
|
||||
pre_pdf = mpdr3 & 0x7;
|
||||
pdf = (mpdr3>>3) & 0x7;
|
||||
pdf = mpdr3 & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
|
||||
break;
|
||||
case ESDHC2_CLK:
|
||||
clk_sel = mpdr3 & 0x40;
|
||||
pre_pdf = (mpdr3 >> 8) & 0x7;
|
||||
pdf = (mpdr3 >> 11) & 0x7;
|
||||
pdf = (mpdr3 >> 8) & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
|
||||
break;
|
||||
case ESDHC3_CLK:
|
||||
clk_sel = mpdr3 & 0x40;
|
||||
pre_pdf = (mpdr3 >> 16) & 0x7;
|
||||
pdf = (mpdr3 >> 19) & 0x7;
|
||||
pdf = (mpdr3 >> 16) & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
|
||||
break;
|
||||
case SPDIF_CLK:
|
||||
clk_sel = mpdr3 & 0x400000;
|
||||
pre_pdf = (mpdr3 >> 29) & 0x7;
|
||||
pdf = (mpdr3 >> 23) & 0x3F;
|
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
||||
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
|
||||
((pre_pdf + 1) * (pdf + 1));
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
/* General purpose timers bitfields */
|
||||
#define GPTCR_SWR (1<<15) /* Software reset */
|
||||
#define GPTCR_FRR (1<<9) /* Freerun / restart */
|
||||
#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
|
||||
#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
|
||||
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
|
||||
#define GPTCR_TEN (1) /* Timer enable */
|
||||
|
||||
#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK)
|
||||
|
||||
/*
|
||||
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
|
||||
* "tick" is internal timer period
|
||||
*/
|
||||
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, TIMER_FREQ_HZ);
|
||||
do_div(tick, MXC_CLK32);
|
||||
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long usec)
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
|
||||
{
|
||||
usec *= TIMER_FREQ_HZ;
|
||||
do_div(usec, 1000000);
|
||||
us = us * MXC_CLK32 + 999999;
|
||||
do_div(us, 1000000);
|
||||
|
||||
return usec;
|
||||
return us;
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing really to do with interrupts, just starts up a counter.
|
||||
* The 32KHz 32-bit timer overruns in 134217 seconds
|
||||
*/
|
||||
int timer_init(void)
|
||||
{
|
||||
int i;
|
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
|
||||
|
||||
/* setup GP Timer 1 */
|
||||
writel(GPTCR_SWR, &gpt->ctrl);
|
||||
for (i = 0; i < 100; i++)
|
||||
writel(0, &gpt->ctrl); /* We have no udelay by now */
|
||||
|
||||
writel(0, &gpt->pre);
|
||||
/* Freerun Mode, PERCLK1 input */
|
||||
writel(readl(&gpt->ctrl) |
|
||||
GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
|
||||
&gpt->ctrl);
|
||||
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
|
||||
|
||||
for (i = 0; i < 100; i++)
|
||||
writel(0, &gpt->ctrl); /* We have no udelay by now */
|
||||
writel(0, &gpt->pre); /* prescaler = 1 */
|
||||
/* Freerun Mode, 32KHz input */
|
||||
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
|
||||
&gpt->ctrl);
|
||||
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -101,7 +111,7 @@ ulong get_timer_masked(void)
|
||||
{
|
||||
/*
|
||||
* get_ticks() returns a long long (64 bit), it wraps in
|
||||
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
|
||||
* 5 * 10^6 days - long enough.
|
||||
*/
|
||||
@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return TIMER_FREQ_HZ;
|
||||
return MXC_CLK32;
|
||||
}
|
||||
|
||||
@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
|
||||
static ulong imx_get_mpllclk(void)
|
||||
{
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong fref = 24000000;
|
||||
ulong fref = MXC_HCLK;
|
||||
|
||||
return imx_decode_pll(readl(&ccm->mpctl), fref);
|
||||
}
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
#include <div64.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, CONFIG_MX25_CLK32);
|
||||
do_div(tick, MXC_CLK32);
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long time_to_tick(unsigned long long time)
|
||||
{
|
||||
time *= CONFIG_MX25_CLK32;
|
||||
time *= MXC_CLK32;
|
||||
do_div(time, CONFIG_SYS_HZ);
|
||||
return time;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
|
||||
{
|
||||
us = us * CONFIG_MX25_CLK32 + 999999;
|
||||
us = us * MXC_CLK32 + 999999;
|
||||
do_div(us, 1000000);
|
||||
return us;
|
||||
}
|
||||
#else
|
||||
/* ~2% error */
|
||||
#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
|
||||
CONFIG_SYS_HZ)
|
||||
#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32)
|
||||
#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
|
||||
#define US_PER_TICK (1000000 / MXC_CLK32)
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
@ -144,7 +144,7 @@ ulong get_timer_masked(void)
|
||||
{
|
||||
/*
|
||||
* get_ticks() returns a long long (64 bit), it wraps in
|
||||
* 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
|
||||
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
|
||||
* 5 * 10^6 days - long enough.
|
||||
*/
|
||||
@ -177,6 +177,6 @@ ulong get_tbclk(void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
tbclk = CONFIG_MX25_CLK32;
|
||||
tbclk = MXC_CLK32;
|
||||
return tbclk;
|
||||
}
|
||||
|
||||
@ -38,12 +38,14 @@
|
||||
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
|
||||
* code simple, it doesn't take rolling into consideration.
|
||||
*/
|
||||
#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
|
||||
void early_delay(int delay)
|
||||
{
|
||||
uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
|
||||
struct mxs_digctl_regs *digctl_regs =
|
||||
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
|
||||
|
||||
uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
|
||||
st += delay;
|
||||
while (st > readl(HW_DIGCTRL_MICROSECONDS))
|
||||
while (st > readl(&digctl_regs->hw_digctl_microseconds))
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)libimx-common.o
|
||||
|
||||
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
|
||||
COBJS-y = iomux-v3.o timer.o cpu.o speed.o
|
||||
COBJS-$(CONFIG_I2C_MXC) += i2c.o
|
||||
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
|
||||
endif
|
||||
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
|
||||
COBJS := $(sort $(COBJS-y))
|
||||
|
||||
@ -26,6 +26,20 @@
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_MX25_HCLK_FREQ
|
||||
#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
|
||||
#else
|
||||
#define MXC_HCLK 24000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX25_CLK32
|
||||
#define MXC_CLK32 CONFIG_MX25_CLK32
|
||||
#else
|
||||
#define MXC_CLK32 32768
|
||||
#endif
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_CSI_CLK,
|
||||
MXC_EPIT_CLK,
|
||||
|
||||
@ -24,6 +24,20 @@
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_MX31_HCLK_FREQ
|
||||
#define MXC_HCLK CONFIG_MX31_HCLK_FREQ
|
||||
#else
|
||||
#define MXC_HCLK 26000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX31_CLK32
|
||||
#define MXC_CLK32 CONFIG_MX31_CLK32
|
||||
#else
|
||||
#define MXC_CLK32 32768
|
||||
#endif
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK,
|
||||
MXC_IPG_CLK,
|
||||
|
||||
@ -24,6 +24,20 @@
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_MX35_HCLK_FREQ
|
||||
#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
|
||||
#else
|
||||
#define MXC_HCLK 24000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX35_CLK32
|
||||
#define MXC_CLK32 CONFIG_MX35_CLK32
|
||||
#else
|
||||
#define MXC_CLK32 32768
|
||||
#endif
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK,
|
||||
MXC_AHB_CLK,
|
||||
|
||||
@ -32,8 +32,8 @@
|
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
|
||||
#define MXC_CCM_CCMR_ROMW_OFFSET 18
|
||||
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCMR_RAMW_OFFSET 21
|
||||
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
|
||||
#define MXC_CCM_CCMR_RAMW_OFFSET 16
|
||||
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCMR_LPM_OFFSET 14
|
||||
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCMR_UPE (1 << 9)
|
||||
@ -47,7 +47,7 @@
|
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
|
||||
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
|
||||
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
|
||||
#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
|
||||
#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
|
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
|
||||
#define MXC_CCM_PDR0_AUTO_CON 0x1
|
||||
@ -62,10 +62,8 @@
|
||||
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
|
||||
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
|
||||
#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
|
||||
#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
|
||||
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
|
||||
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
|
||||
@ -78,35 +76,23 @@
|
||||
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
|
||||
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
|
||||
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
|
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
|
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_PDR3_UART_M_U (1 << 15)
|
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
|
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR3_UART_M_U (1 << 14)
|
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
|
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
|
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
|
||||
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
|
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
|
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
|
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
|
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
|
||||
|
||||
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
|
||||
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
|
||||
#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
|
||||
#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
|
||||
#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
|
||||
#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
|
||||
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
|
||||
#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
|
||||
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
|
||||
#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
|
||||
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
|
||||
|
||||
/* Bit definitions for RCSR */
|
||||
@ -144,6 +130,12 @@
|
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
|
||||
|
||||
/* Bit definitions for Clock gating Register*/
|
||||
#define MXC_CCM_CGR_CG_MASK 0x3
|
||||
#define MXC_CCM_CGR_CG_OFF 0x0
|
||||
#define MXC_CCM_CGR_CG_RUN_ON 0x1
|
||||
#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
|
||||
#define MXC_CCM_CGR_CG_ON 0x3
|
||||
|
||||
#define MXC_CCM_CGR0_ASRC_OFFSET 0
|
||||
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
|
||||
#define MXC_CCM_CGR0_ATA_OFFSET 2
|
||||
@ -251,10 +243,8 @@
|
||||
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
|
||||
#define MXC_CCM_COSR_CLKOEN (1 << 5)
|
||||
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
|
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10)
|
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10
|
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13)
|
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13
|
||||
#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
|
||||
#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
|
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
|
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
|
||||
|
||||
@ -34,21 +34,21 @@
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24)
|
||||
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19)
|
||||
#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
|
||||
#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
|
||||
@ -63,55 +63,55 @@
|
||||
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
|
||||
#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7)
|
||||
#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2)
|
||||
#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2)
|
||||
|
||||
#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
|
||||
#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
|
||||
|
||||
@ -173,7 +173,7 @@ const iomux_cfg_t iomux_setup[] = {
|
||||
#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
|
||||
ADDR_PINS << 8 | APREBIT)
|
||||
|
||||
void mx28_adjust_memory_params(uint32_t *dram_vals)
|
||||
void mxs_adjust_memory_params(uint32_t *dram_vals)
|
||||
{
|
||||
dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
|
||||
}
|
||||
|
||||
@ -49,8 +49,8 @@ int board_early_init_f(void)
|
||||
|
||||
/* SSP0 clock at 96MHz */
|
||||
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
||||
/* SSP2 clock at 96MHz */
|
||||
mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
|
||||
/* SSP2 clock at 160MHz */
|
||||
mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
|
||||
|
||||
@ -71,91 +71,17 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf
|
||||
Flashing U-Boot
|
||||
--------------------------------
|
||||
|
||||
There are two options: the original bootloader in NAND can be replaced with
|
||||
u-boot, or u-boot can be stored on the NOR flash without erasing
|
||||
the delivered bootloader.
|
||||
U-boot should be stored on the NOR flash.
|
||||
|
||||
The boot storage can be select using the switches on the personality board
|
||||
(SW1-SW2) and on the DEBUG board (SW4-SW10).
|
||||
|
||||
The second option is to be preferred if you have not a JTAG debugger.
|
||||
If something goes wrong flashing the bootloader, it is always possible to
|
||||
recover the board booting from the other device.
|
||||
|
||||
Replacing the bootloader on the NAND
|
||||
--------------------------------------
|
||||
To replace RedBoot with U-Boot, the easy way is to do this in linux.
|
||||
Start the kernel with the suggested options. Make sure to have set the
|
||||
mtdparts exactly as described, because this matches the layout on the
|
||||
mx35pdk.
|
||||
|
||||
You should see in your boot log the following entries for the NAND
|
||||
flash:
|
||||
|
||||
5 cmdlinepart partitions found on MTD device mxc_nand
|
||||
Creating 5 MTD partitions on "mxc_nand":
|
||||
0x000000000000-0x000000100000 : "boot"
|
||||
0x000000100000-0x000000600000 : "linux"
|
||||
0x000000600000-0x000006600000 : "root"
|
||||
0x000006600000-0x000006e00000 : "cfg"
|
||||
0x000006e00000-0x000080000000 : "user"
|
||||
|
||||
You can use the utilities flash_eraseall and nandwrite to put
|
||||
u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
|
||||
reserved. If everything is correct, this partition is accessed as
|
||||
/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
|
||||
get the device node from the partition name:
|
||||
|
||||
$ cat /proc/mtd | grep boot
|
||||
|
||||
I suggest you try the utilities on a different partition to be sure
|
||||
if everything works correctly. If not, and you remove RedBoot, you have to
|
||||
reinstall it using the ATK tool as suggested by Freescale, or using a
|
||||
JTAG debugger.
|
||||
|
||||
I report the versions of the utilities I used (they are provided with ELDK):
|
||||
|
||||
-bash-3.2# nandwrite --version
|
||||
nandwrite $Revision: 1.32 $
|
||||
|
||||
flash_eraseall --version
|
||||
flash_eraseall $Revision: 1.22 $
|
||||
|
||||
nandwrite reports a warning if the file to be saved is not sector aligned.
|
||||
This should have no consequences, but I preferred to pad u-boot.bin
|
||||
to get no problem at all.
|
||||
$ dd if=/dev/zero of=zeros bs=1 count=74800
|
||||
$ cat u-boot.bin zeros > u-boot-padded.bin
|
||||
|
||||
To erase the partition:
|
||||
$ flash_eraseall /dev/mtd4
|
||||
|
||||
Writing u-boot:
|
||||
|
||||
$ nandwrite /dev/mtd4 u-boot-padded.bin
|
||||
|
||||
Now U-Boot is stored on the booting partition.
|
||||
|
||||
To boot from NAND, you have to select the switches as follows:
|
||||
|
||||
Personality board
|
||||
SW2 1, 4, 5 on
|
||||
2, 3, 6, 7, 8 off
|
||||
SW1 all off
|
||||
|
||||
Debug Board:
|
||||
SW5 0
|
||||
SW6 0
|
||||
SW7 0
|
||||
SW8 1
|
||||
SW9 1
|
||||
SW10 0
|
||||
|
||||
|
||||
Saving U-Boot in the NOR flash
|
||||
---------------------------------
|
||||
|
||||
The procedure to save in the NOR flash is quite the same as to write into the NAND.
|
||||
|
||||
Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
|
||||
the boot partition should be /dev/mtd0.
|
||||
|
||||
|
||||
@ -32,6 +32,8 @@
|
||||
#include <i2c.h>
|
||||
#include <pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mc9sdz60.h>
|
||||
#include <mc13892.h>
|
||||
#include <linux/types.h>
|
||||
@ -275,3 +277,26 @@ int board_eth_init(bd_t *bis)
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
|
||||
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/* configure pins for SDHC1 only */
|
||||
mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -197,18 +197,18 @@ static iomux_v3_cfg_t button_pads[] = {
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
gpio_direction_output(87, 0); /* GPIO 3-23 */
|
||||
gpio_direction_output(190, 1); /* GPIO 6-30 */
|
||||
gpio_direction_output(185, 1); /* GPIO 6-25 */
|
||||
gpio_direction_output(187, 1); /* GPIO 6-27 */
|
||||
gpio_direction_output(188, 1); /* GPIO 6-28*/
|
||||
gpio_direction_output(189, 1); /* GPIO 6-29 */
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
|
||||
gpio_direction_output(184, 1); /* GPIO 6-24 */
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
|
||||
|
||||
/* Need delay 10ms according to KSZ9021 spec */
|
||||
udelay(1000 * 10);
|
||||
gpio_set_value(87, 1); /* GPIO 3-23 */
|
||||
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
|
||||
}
|
||||
@ -249,11 +249,11 @@ int board_mmc_getcd(struct mmc *mmc)
|
||||
int ret;
|
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
gpio_direction_input(192); /*GPIO7_0*/
|
||||
ret = !gpio_get_value(192);
|
||||
gpio_direction_input(IMX_GPIO_NR(7, 0));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
|
||||
} else {
|
||||
gpio_direction_input(38); /*GPIO2_6*/
|
||||
ret = !gpio_get_value(38);
|
||||
gpio_direction_input(IMX_GPIO_NR(2, 6));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
@ -27,11 +27,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := efikamx.o
|
||||
|
||||
ifdef CONFIG_CMD_USB
|
||||
COBJS += efikamx-usb.o
|
||||
endif
|
||||
COBJS := efikamx.o efikamx-usb.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@ -214,3 +214,15 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
|
||||
if (port)
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ethernet on the Smarttop is on the USB bus. Rather than give an error about
|
||||
* "CPU Net Initialization Failed", just pass this test since no other settings
|
||||
* are required. Smartbook doesn't have built-in Ethernet but we will let it
|
||||
* pass anyway considering someone may have plugged in a USB stick and all
|
||||
* they need to do is run "usb start".
|
||||
*/
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -492,9 +492,6 @@ int board_late_init(void)
|
||||
ARRAY_SIZE(efikamx_pata_pads));
|
||||
setup_iomux_usb();
|
||||
|
||||
if (machine_is_efikasb())
|
||||
setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -119,6 +119,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
|
||||
(uint32_t)(priv->desc->cmd.address + cache_data_count));
|
||||
}
|
||||
|
||||
/* Invalidate the area, so no writeback into the RAM races with DMA */
|
||||
invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
|
||||
(uint32_t)(priv->desc->cmd.address + cache_data_count));
|
||||
|
||||
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
|
||||
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
|
||||
|
||||
|
||||
@ -224,8 +224,10 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
||||
struct mxs_dma_desc *dp;
|
||||
uint32_t ctrl0;
|
||||
uint32_t cache_data_count;
|
||||
const uint32_t dstart = (uint32_t)data;
|
||||
int dmach;
|
||||
int tl;
|
||||
int ret = 0;
|
||||
|
||||
ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
|
||||
|
||||
@ -239,17 +241,17 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
||||
if (!write)
|
||||
ctrl0 |= SSP_CTRL0_READ;
|
||||
|
||||
writel(length, &ssp_regs->hw_ssp_xfer_size);
|
||||
|
||||
if (length % ARCH_DMA_MINALIGN)
|
||||
cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
|
||||
else
|
||||
cache_data_count = length;
|
||||
|
||||
/* Flush data to DRAM so DMA can pick them up */
|
||||
if (write)
|
||||
/* Flush data to DRAM so DMA can pick them up */
|
||||
flush_dcache_range((uint32_t)data,
|
||||
(uint32_t)(data + cache_data_count));
|
||||
flush_dcache_range(dstart, dstart + cache_data_count);
|
||||
|
||||
/* Invalidate the area, so no writeback into the RAM races with DMA */
|
||||
invalidate_dcache_range(dstart, dstart + cache_data_count);
|
||||
|
||||
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
|
||||
|
||||
@ -281,41 +283,47 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
||||
tl = min(length, xfer_max_sz);
|
||||
|
||||
dp->cmd.data |=
|
||||
(tl << MXS_DMA_DESC_BYTES_OFFSET) |
|
||||
(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
|
||||
((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
|
||||
(4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
|
||||
MXS_DMA_DESC_HALT_ON_TERMINATE |
|
||||
MXS_DMA_DESC_TERMINATE_FLUSH;
|
||||
dp->cmd.pio_words[0] = ctrl0;
|
||||
|
||||
data += tl;
|
||||
length -= tl;
|
||||
|
||||
if (!length) {
|
||||
dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
|
||||
|
||||
if (flags & SPI_XFER_END) {
|
||||
ctrl0 &= ~SSP_CTRL0_LOCK_CS;
|
||||
ctrl0 |= SSP_CTRL0_IGNORE_CRC;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
|
||||
* essential that the XFER_SIZE register is written on
|
||||
* a per-descriptor basis with the same size as is the
|
||||
* descriptor!
|
||||
*/
|
||||
dp->cmd.pio_words[0] = ctrl0;
|
||||
dp->cmd.pio_words[1] = 0;
|
||||
dp->cmd.pio_words[2] = 0;
|
||||
dp->cmd.pio_words[3] = tl;
|
||||
|
||||
mxs_dma_desc_append(dmach, dp);
|
||||
|
||||
dp++;
|
||||
}
|
||||
|
||||
dp->address = (dma_addr_t)dp;
|
||||
dp->cmd.address = (dma_addr_t)0;
|
||||
dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER |
|
||||
(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
|
||||
MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
|
||||
if (flags & SPI_XFER_END) {
|
||||
ctrl0 &= ~SSP_CTRL0_LOCK_CS;
|
||||
dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
|
||||
}
|
||||
mxs_dma_desc_append(dmach, dp);
|
||||
|
||||
if (mxs_dma_go(dmach))
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
|
||||
/* The data arrived into DRAM, invalidate cache over them */
|
||||
if (!write) {
|
||||
invalidate_dcache_range((uint32_t)data,
|
||||
(uint32_t)(data + cache_data_count));
|
||||
}
|
||||
if (!write)
|
||||
invalidate_dcache_range(dstart, dstart + cache_data_count);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||
|
||||
@ -31,7 +31,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX35
|
||||
#define CONFIG_MX35_HCLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
@ -64,7 +64,6 @@
|
||||
/* Ethernet on FEC */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
@ -72,7 +71,7 @@
|
||||
#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR
|
||||
#define CONFIG_RESET_PHY_R
|
||||
#define CONFIG_FEC_MXC_NO_ANEG
|
||||
#define CONFIG_PRIME "FEC0"
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_HARD_SPI
|
||||
|
||||
@ -33,7 +33,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX31 1 /* in a mx31 */
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000
|
||||
#define CONFIG_MX31_CLK32 32000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
@ -33,7 +33,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX31 /* in a mx31 */
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000
|
||||
#define CONFIG_MX31_CLK32 32000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
@ -171,9 +171,9 @@
|
||||
#define CONFIG_LZO
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define MTDIDS_DEFAULT "nand0=gpmi-nand.0"
|
||||
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=gpmi-nand.0:" \
|
||||
"mtdparts=gpmi-nand:" \
|
||||
"3m(bootloader)ro," \
|
||||
"512k(environment)," \
|
||||
"512k(redundant-environment)," \
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x81200000
|
||||
|
||||
|
||||
@ -184,6 +184,9 @@
|
||||
#define CONFIG_EHCI_MXS_PORT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_USB_ETHER_SMSC95XX
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
@ -199,6 +202,7 @@
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_MXS_SPI
|
||||
#define CONFIG_MXS_SPI_DMA_ENABLE
|
||||
#define CONFIG_SPI_HALF_DUPLEX
|
||||
#define CONFIG_DEFAULT_SPI_BUS 2
|
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||
@ -235,7 +239,6 @@
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTCOMMAND "run bootcmd_net"
|
||||
#define CONFIG_LOADADDR 0x42000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_OF_LIBFDT
|
||||
@ -244,13 +247,80 @@
|
||||
* Extra Environments
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console_fsl=console=ttyAM0" \
|
||||
"console_mainline=console=ttyAMA0" \
|
||||
"netargs=setenv bootargs console=${console_mainline}" \
|
||||
"update_nand_full_filename=u-boot.nand\0" \
|
||||
"update_nand_firmware_filename=u-boot.sb\0" \
|
||||
"update_sd_firmware_filename=u-boot.sd\0" \
|
||||
"update_nand_firmware_maxsz=0x100000\0" \
|
||||
"update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
|
||||
"update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
|
||||
"update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
|
||||
"nand device 0 ; " \
|
||||
"nand info ; " \
|
||||
"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
|
||||
"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
|
||||
"update_nand_full=" /* Update FCB, DBBT and FW */ \
|
||||
"if tftp ${update_nand_full_filename} ; then " \
|
||||
"run update_nand_get_fcb_size ; " \
|
||||
"nand scrub -y 0x0 ${filesize} ; " \
|
||||
"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
|
||||
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
|
||||
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
|
||||
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
|
||||
"fi\0" \
|
||||
"update_nand_firmware=" /* Update only firmware */ \
|
||||
"if tftp ${update_nand_firmware_filename} ; then " \
|
||||
"run update_nand_get_fcb_size ; " \
|
||||
"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
|
||||
"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
|
||||
"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
|
||||
"nand erase ${fcb_sz} ${fw_sz} ; " \
|
||||
"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
|
||||
"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
|
||||
"fi\0" \
|
||||
"update_sd_firmware=" /* Update the SD firmware partition */ \
|
||||
"if mmc rescan ; then " \
|
||||
"if tftp ${update_sd_firmware_filename} ; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
|
||||
"setexpr fw_sz ${fw_sz} + 1 ; " \
|
||||
"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console_fsl=ttyAM0\0" \
|
||||
"console_mainline=ttyAMA0\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=2\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rw\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm\0" \
|
||||
"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
|
||||
"bootcmd_net=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"dhcp ${uimage}; bootm\0" \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"dhcp ${uimage}; bootm\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc rescan ${mmcdev}; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
#endif /* __MX28EVK_CONFIG_H__ */
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX31 1 /* in a mx31 */
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
|
||||
#define CONFIG_MX31_CLK32 32768
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
@ -35,8 +35,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX31 /* in a mx31 */
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000
|
||||
#define CONFIG_MX31_CLK32 32768
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
@ -31,7 +31,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX35
|
||||
#define CONFIG_MX35_HCLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
@ -111,6 +110,12 @@
|
||||
#define CONFIG_NET_RETRY_COUNT 100
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
|
||||
@ -238,6 +243,13 @@
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
|
||||
/* mmc driver */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
/*
|
||||
* Default environment and default scripts
|
||||
* to update uboot and load kernel
|
||||
@ -279,8 +291,8 @@
|
||||
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
|
||||
"update=protect off ${uboot_addr} +40000;" \
|
||||
"erase ${uboot_addr} +40000;" \
|
||||
"update=protect off ${uboot_addr} +80000;" \
|
||||
"erase ${uboot_addr} +80000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
|
||||
@ -28,8 +28,6 @@
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX31 /* in a mx31 */
|
||||
#define CONFIG_QONG
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
|
||||
#define CONFIG_MX31_CLK32 32768
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
@ -39,8 +39,6 @@
|
||||
#include <asm/arch/regs-base.h>
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
@ -31,8 +31,6 @@
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136
|
||||
#define CONFIG_MX31
|
||||
#define CONFIG_MX31_HCLK_FREQ 26000000
|
||||
#define CONFIG_MX31_CLK32 32768
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
@ -28,7 +28,6 @@
|
||||
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_MX25
|
||||
#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_TEXT_BASE 0xA0000000
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user