We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add system manager register struct and macros for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Commit ce62e57fc5 ("ARM: boot0 hook: remove macro, include whole
header file") miss out cleaning macro in this header file, and this
has broken implementation of a boot header capability in socfpga
SPL. Remove the macro in this file, and recovering it back
to proper functioning.
Fixes: ce62e57fc5 ("ARM: boot0 hook: remove macro, include whole
header file")
Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
the socfpga bootrom supports mmc booting from either a raw image
starting at 0x0, or from a partition of type 0xa2. This patch
adds support for locating the boot image in the first type 0xa2
partition found.
Assigned a partition number of -1 will cause a search for a
partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
and use it to find the u-boot image
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This option should not really be user selectable. Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.
Signed-off-by: Bill Randle <bill.randle@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.
The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:
ffff0040 <data_abort>:
ffff0040: ebfffffe bl ffff0040 <data_abort>
ffff0044 <reset>:
ffff0044: ea000012 b ffff0094 <save_boot_params>
ffff0048 <save_boot_params_ret>:
ffff0048: e10f0000 mrs r0, CPSR
ffff004c: e200101f and r1, r0, #31
ffff0050: e331001a teq r1, #26
Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.
Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cover-Letter: Fixes several spelling errors for the words "resetting",
"extended", "occur", and "multiple".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
Just sort the board entries, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.
Signed-off-by: Pavel Machek <pavel@denx.de>
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.
This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The following patch caused cpu_eth_init() to not be called anymore
for DM-capable boards:
commit c32a6fd07b
Date: Sun Jan 17 14:51:56 2016 -0700
net: Don't call board/cpu_eth_init() with driver model
This breaks ethernet on SoCFPGA, since we use that function to un-reset
the ethernet blocks. Invoke the ethernet reset function from arch_misc_init()
instead to fix the breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Weed out bashisms from the script. The echo -e does not work in dash,
which is the default /bin/sh in debian .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
The hps_isw_handoff and bsp/generated folders are typically not in the same
path.This patch adds support for specifying the different input directories for
the bsp and quartus projects.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
If the system boots from NAND, make sure to de-assert the NAND IP
reset, otherwise the system will get stuck.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Define the NAND reset bit and fix the ordering of the macros.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The L2 cache was never enabled in the v7_outer_cache_enable(), fix
this and enable the L2 cache.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Move the macro into the socfpga_dwmci_clksel().
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The SoCFPGA has reached a point where every single board code become
the same, since each and every single board is probed equally from OF.
Move the common board code into arch/arm/mach-socfpga/ .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This function triggers the registration of the dwmmc driver on SoCFPGA,
but this is not needed in case the driver is correctly probed from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:
- SPI NOR
- eMMC
- Ethernet
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.
Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map
Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is also supported.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add support for DENX MCV SoM, which is CycloneV based and the
associated DENX MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the SoCFPGA SPL with the correct SPL design as well as reduces
the stack utilisation slightly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.
This patch now also removes previous temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Signed-off-by: Marek Vasut <marex@denx.de>
Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.
Signed-off-by: Marek Vasut <marex@denx.de>
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: Marek Vasut <marex@denx.de>
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.
All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.
The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Signed-off-by: Marek Vasut <marex@denx.de>
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Signed-off-by: Marek Vasut <marex@denx.de>
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.
Signed-off-by: Marek Vasut <marex@denx.de>
Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code
uses the scan manager to send jtag pulses that will return the FPGA ID.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Factor out the code which sends JTAG instruction followed by data
into separate function to tidy the code up a little.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Clean up the horrible macros present in the scan_manager.h . Firstly,
the function scan_mgr_io_scan_chain_prg() is static, yet all the macros
are used only within it, thus there is no point in having them in the
header file. Moreover, the macros are just making the code much less
readable, so remove them instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce generic function for accessing the JTAG scan chains in the
SCC manager. Make use of this function throughout the SCC manager to
replace the ad-hoc writes to registers and make the code less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework this function so it's clear that it is only polling for certain
bits to be cleared. Add kerneldoc. Fix it's return value to be either
0 on success and -ETIMEDOUT on error and propagate this through the
scan manager code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Zap non-existent functions and place function prototypes at the
beginning of the header file.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Add a small workaround into the platform code which forces the SDMMC
into 8-bit mode (the default configuration for all socfpga platforms)
to work around breakage caused by missing patches in mainline which
switch the probing of SD/MMC to OF instead of static configuraiton.
The patches will hit mainline after the SPL series, so to avoid build
issues, add this small temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The GMAC can now be probed from OF, so enable DM ethernet and remove the
old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: Marek Vasut <marex@denx.de>
