Marek Vasut 65d372c44c arm: socfpga: Assure ISWGRP 0 and 1 are inited ... This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>		2015-09-04 11:54:20 +02:00
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include/mach	mmc: dw_mmc: Probe the MMC from OF	2015-09-04 11:54:20 +02:00
clock_manager.c	arm: socfpga: Fix delay in clock manager	2015-08-23 11:56:19 +02:00
fpga_manager.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00
freeze_controller.c	arm: socfpga: Fix delay in freeze controller	2015-08-23 11:56:19 +02:00
Kconfig	arm: socfpga: Split Altera socfpga into AV and CV SoCDK	2015-08-23 11:56:19 +02:00
Makefile	arm: socfpga: Move wrappers into platform directory	2015-08-23 11:56:19 +02:00
misc.c	mmc: dw_mmc: Probe the MMC from OF	2015-09-04 11:54:20 +02:00
qts-filter.sh	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
reset_manager.c	arm: socfpga: Assure ISWGRP 0 and 1 are inited	2015-09-04 11:54:20 +02:00
scan_manager.c	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
spl.c	arm: socfpga: config: Move SPL GD and malloc to RAM	2015-08-08 14:14:09 +02:00
system_manager.c	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
timer.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00
wrap_iocsr_config.c	arm: socfpga: Switch to filtered QTS files	2015-08-23 11:56:20 +02:00
wrap_pinmux_config.c	arm: socfpga: Make the pinmux table const u8	2015-08-23 11:56:20 +02:00
wrap_pll_config.c	arm: socfpga: Move wrappers into platform directory	2015-08-23 11:56:19 +02:00
wrap_sdram_config.c	arm: socfpga: Switch to filtered QTS files	2015-08-23 11:56:20 +02:00