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89a54abf1b
u-boot-brain/arch/arm/mach-socfpga
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Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters 
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:07 +02:00
..
include/mach ddr: altera: Configuring SDRAM extra cycles timing parameters 2016-10-27 08:03:07 +02:00
board.c arm: socfpga: Introduce common board code 2015-12-20 03:36:51 +01:00
clock_manager.c arm: socfpga: Fix delay in clock manager 2015-08-23 11:56:19 +02:00
fpga_manager.c treewide: replace #include <asm/errno.h> with <linux/errno.h> 2016-09-23 17:55:42 -04:00
freeze_controller.c treewide: replace #include <asm/errno.h> with <linux/errno.h> 2016-09-23 17:55:42 -04:00
Kconfig Convert CONFIG_SPL_WATCHDOG_SUPPORT to Kconfig 2016-09-16 17:27:23 -04:00
Makefile arm: socfpga: remove building scan manager 2015-12-20 03:44:56 +01:00
misc.c socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled 2016-05-06 18:41:49 +02:00
qts-filter.sh ddr: altera: Configuring SDRAM extra cycles timing parameters 2016-10-27 08:03:07 +02:00
reset_manager.c arm: socfpga: Assure ISWGRP 0 and 1 are inited 2015-09-04 11:54:20 +02:00
scan_manager.c arm: socfpga: scan: Add code to get FPGA ID 2015-08-08 14:14:30 +02:00
spl.c common: Pass the boot device into spl_boot_mode() 2016-06-26 20:17:22 +02:00
system_manager.c arm: socfpga: Make the pinmux table const u8 2015-08-23 11:56:20 +02:00
timer.c ARM: socfpga: move SoC sources to mach-socfpga 2015-05-07 05:21:12 +02:00
wrap_iocsr_config.c arm: socfpga: Switch to filtered QTS files 2015-08-23 11:56:20 +02:00
wrap_pinmux_config.c arm: socfpga: Make the pinmux table const u8 2015-08-23 11:56:20 +02:00
wrap_pll_config.c arm: socfpga: Move wrappers into platform directory 2015-08-23 11:56:19 +02:00
wrap_sdram_config.c ddr: altera: Configuring SDRAM extra cycles timing parameters 2016-10-27 08:03:07 +02:00