Marek Vasut a8535c306c arm: socfpga: Fix delay in freeze controller ... Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>		2015-08-23 11:56:19 +02:00
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include/mach	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
clock_manager.c	arm: socfpga: clock: Clean up pll_config.h	2015-08-08 14:14:06 +02:00
fpga_manager.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00
freeze_controller.c	arm: socfpga: Fix delay in freeze controller	2015-08-23 11:56:19 +02:00
Kconfig	arch: Make board selection choices optional	2015-05-12 18:10:02 -04:00
Makefile	arm: socfpga: misc: Add support for printing FPGA type	2015-08-08 14:14:30 +02:00
misc.c	arm: socfpga: misc: Add support for printing FPGA type	2015-08-08 14:14:30 +02:00
reset_manager.c	arm: socfpga: reset: Add function to reset add peripherals	2015-08-08 14:14:06 +02:00
scan_manager.c	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
spl.c	arm: socfpga: config: Move SPL GD and malloc to RAM	2015-08-08 14:14:09 +02:00
system_manager.c	arm: socfpga: system: Clean up pinmux_config.c	2015-08-08 14:14:07 +02:00
timer.c	ARM: socfpga: move SoC sources to mach-socfpga	2015-05-07 05:21:12 +02:00