Commit Graph

53525 Commits

Author SHA1 Message Date
Lukas Auer
111ab36fb6 riscv: qemu: enable distro boot
Enable distro boot on the qemu-riscv32/64 boards. Supported boot target
devices are VirtIO and DHCP.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-11-26 13:57:33 +08:00
Lukas Auer
a8da9ff466 distro_bootcmd: add VirtIO distro boot command
Add a boot command to distro boot to support disks connected over the
VirtIO bus. The boot command uses the shared block environment.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-11-26 13:57:32 +08:00
Lukas Auer
c3b1a99040 riscv: align bootm implementation with that of other architectures
The bootm implementation of RISC-V diverges from that of other
architectures. Update it to match the implementation of other
architectures. The ARM implementation is used as a reference.

This adds the following features and changes to RISC-V.
* Add support for the BOOTM_STATE_OS_FAKE_GO command
* Call the remove function on devices with the removal flag set before
booting Linux
* Force disconnect USB devices from the host before booting Linux
* Print and add bootstage information to the device tree before booting
Linux

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
52b984369f riscv: qemu: support booting Linux
Support booting Linux (as payload of BBL) from FIT images. For this, the
default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment
variables fdt_high and initrd_high are set to mark the device tree and
initrd as in-place.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
6e10e94ff7 riscv: qemu: use device tree passed by prior boot stage
QEMU provides a device tree, which is passed to U-Boot using register
a1. We are now able to directly select the device tree with the
configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in
qemu-riscv with it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
5d8b2e7711 riscv: save hart ID and device tree passed by prior boot stage
Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.

The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
31f9058994 riscv: do not blindly modify the mstatus CSR
The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.

This instruction and others encode zero as an immediate.  RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
8bfa231cc6 riscv: remove unused labels in start.S
The labels nmi_vector, trap_vector and handle_reset in start.S are not
used for RISC-V. Remove them.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:32 +08:00
Bin Meng
c95cafd0b1 Drop CONFIG_INIT_CRITICAL
This is now deprecated and no board is using it. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-11-26 13:57:31 +08:00
Lukas Auer
2a23ac6107 riscv: align mtvec on a 4-byte boundary
The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
c55309c091 riscv: fix inconsistent use of spaces and tabs in start.S
start.S uses both tabs and spaces after instructions. Fix this by only
using tabs after instructions.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
62a09ad53b riscv: implement the invalidate_icache_* functions
Implement the functions invalidate_icache_range() and
invalidate_icache_all().

RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
c93a1c8185 riscv: hang on unhandled exceptions
Hang on unhandled exceptions to prevent execution in a faulty state.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
e8b522b1df riscv: treat undefined exception codes as reserved
Undefined exception codes currently lead to an out-of-bounds array
access. Prevent this by treating undefined exception codes as
"reserved".

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
5a441736b7 riscv: complete the list of exception codes
Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
f105d2efcb riscv: do not reimplement generic io functions
RISC-V U-Boot reimplements the generic io functions from
asm-generic/io.h. Remove the redundant implementation and include the
generic io.h instead.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
fc8c76f42e riscv: make use of the barrier functions from Linux
Replace the barrier functions in arch/riscv/include/asm/io.h with those
defined in barrier.h, which is imported from Linux. This version is
modified to remove the include statement of asm-generic/barrier.h, which
is not available in U-Boot or required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
b2c860c6dc riscv: fix use of incorrectly sized variables
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
776e6335bf riscv: enable -fdata-sections
Enable the -fdata-sections compiler option for RISC-V. Buildman reports
the binary size decrease from this as 8365.3 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
0c074845e5 riscv: set -march and -mabi based on the Kconfig configuration
Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.

With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
d57ffa650f riscv: add Kconfig entries for the C and A ISA extensions
Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.

The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
711585649e riscv: select CONFIG_PHYS_64BIT on RV64I systems
CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
862e2e75e8 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
17f2ffea36 dts: riscv: update makefile to also clean the RISC-V dts directory
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:28 +08:00
Lukas Auer
07c098b7d6 tools: .gitignore: add prelink-riscv
Ignore tools/prelink-riscv.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:28 +08:00
Tom Rini
5830791d91 Various minor sandbox improvements
Better buildman warning handling
 Misc other things
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Merge tag 'pull-tg18' of git://git.denx.de/u-boot-dm

Various minor sandbox improvements
Better buildman warning handling
Misc other things
2018-11-23 17:25:27 -05:00
Simon Glass
a58986ca8b sf: Add a method to obtain the block-protect setting
It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
f9d49f92f8 test: sf: Add a simple SPI flash test
The current test is a functional test, covering all the way from the
command line to the sandbox SPI driver. This is useful, but it is easier
to diagnose failures with a smaller test.

Add a simple test which reads and writes data and checks that it is stored
and retrieved correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
8729b1ae2c misc: Update read() and write() methods to return bytes xfered
At present these functions return 0 on success. For some devices we want
to know how many bytes were transferred. It seems useful to adjust the API
to be more like the POSIX read() and write() functions.

Update these two methods, a test and all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-20 19:14:22 -07:00
Simon Glass
96794a3eae string: Include the config header
At present the config header is not included in this file, but it does use
a CONFIG option. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
b9f210a35c video: Update video_set_default_colors() to support invert
It is useful to be able to invert the colours in some cases so that the
text matches the background colour. Add a parameter to the function to
support this.

It is strange that function takes a private data structure from another
driver as an argument. It seems better to pass the device and have the
function internally work out how to find its required information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
4b6dbaa307 binman: Set the pathname correctly for ELF files
At present, stripped files don't have the right pathname which means that
blob compression cannot be used. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
26cc8fccc6 binman: Drop an unnecessary comma in blob handling
This comma is not needed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
a3c005506a binman: Add a way to enable debugging from the build
When the build fails due to something wrong in binman it is sometimes
useful to get a full backtrace showing the location of the failure. Add
a BINMAN_DEBUG environment variable to support this along with some
documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
048c6e8956 spl: lz4: Allow use of lz4 compression in SPL
In some cases U-Boot is compressed and it is useful to be able to
decompress it in SPL. Add a Kconfig and Makefile change to allow this.
Note that this does not actually implement decompression.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
c0126bd862 spl: Support bootstage, log, hash and early malloc in TPL
At present these features are supported in SPL but not TPL. Update the
Kconfig and Makefile to allow this.

Also add a few Makefile comments to make earier to track what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
4a5b5e1a46 sandbox: Update some drivers to work in SPL/TPL
At present sandbox drivers are mostly not used before relocation. Some of
these are needed by Chromium OS verified boot, since it uses sandbox TPL,
so update them accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
a2a63a35b2 sandbox: cros_ec: exynos: Drop use of cros_ec_get_error()
This function is really just a call to uclass_get_device() and there is no
reason why the caller cannot do it. Update sandbox and snow accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2018-11-20 19:14:22 -07:00
Simon Glass
566bf3a869 sandbox: Add a function to read a host file
Add a way to read a file from the host filesystem. This can be useful for
reading test data, for example. Also fix up the writing function which was
not the right version, and drop the debugging lines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
a5c13b68e7 sandbox: log: Add a category for sandbox
It seems useful to make sandbox its own log category since it is used for
so much testing. Add this as a new category.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
04488c4d15 sandbox: tpm: Allow debugging of data packages
This is not normally useful, so change the code to avoid writing out every
data package. This can be enabled with #define DEBUG.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
72ef8bfd6d cros_ec: Add new features for events and power
This adds new commands to the EC related to setting and clearing events
as well as controlling power-related settings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
4bf6f2ad47 cros_ec: Align uclass data to a cache boundary
The LPC driver expects its buffer to be word-aligned. Add the required
flag to the uclass driver to ensure this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
dc05ac0f2f cros_ec: Fail if we cannot determine the flash burst size
This value is required for flashing to work correctly. Add a check for
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
ac80652342 cros_ec: Add error logging on a few commands
Add some more logging to provide more information on failures.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
9fea76f5d3 cros_ec: Use uint instead of u8 for parameters
There is no advantage to using a u8 for function parameters. It forces
the compiler to mask values and can increase code size. Also the command
enum has been extended to 16 bits. Update the functions to use uint
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
6af7101b75 buildman: Show boards with warning with w+
At present we should boards with warnings in the same way as those with
errors. This is not ideal. Add a new 'warn' state and show these listed
in yellow to match the actual warning lines printing with -e.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
4cf2b221c6 buildman: Rename the good, better, worse variables
At present we don't distinguish between errors and warnings when printing
the architecture summary. Rename the variables to better describe their
purpose.

'Worse' at present means we got an error, so use that as the name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
2d48333e44 buildman: Detect dtc warnings
At present messages from the device-tree compiler like this:

  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dtb: Warning
     (avoid_unnecessary_addr_size): /clocks: unnecessary
     #address-cells/#size-cells without "ranges" or child "reg" property

are detected as errors since they don't match the gcc warning regex. Add a
new one for dtc to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
40232c91d7 buildman: Only print toolchain probing with -v
At present --list-tool-chains prints a lot of information about the
toolchain-probing process. This is generally not very interesting.
Update buildman to print this only if --list-tool-chains is given
with -v.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00