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riscv: save hart ID and device tree passed by prior boot stage

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Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.

The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Lukas Auer 2018-11-22 11:26:29 +01:00 committed by Andes
parent 31f9058994
commit 5d8b2e7711
2 changed files with 16 additions and 2 deletions
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6
arch/riscv/cpu/cpu.c
View File

@ -6,6 +6,12 @@
#include <common.h>
#include <asm/csr.h>
/*
* prior_stage_fdt_address must be stored in the data section since it is used
* before the bss section is available.
*/
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
enum {
ISA_INVALID = 0,
ISA_32BIT,

12
arch/riscv/cpu/start.S
View File

@ -34,6 +34,10 @@
.section .text
.globl _start
_start:
/* save hart id and dtb pointer */
mv s0, a0
mv s1, a1
li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0)
la t0, trap_entry
@ -58,6 +62,10 @@ call_board_init_f_0:
mv a0, sp
jal board_init_f_alloc_reserve
mv sp, a0
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
jal board_init_f_init_reserve
mv a0, zero /* a0 <-- boot_flags = 0 */
@ -140,8 +148,8 @@ fix_rela_dyn:
LREG t3, -(REGBYTES*3)(t1)
li t5, SYM_SIZE
mul t0, t0, t5
add s1, t4, t0
LREG t5, REGBYTES(s1)
add s5, t4, t0
LREG t5, REGBYTES(s5)
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)