Fixes for 2021.1
---------------- CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680 - fixes for Variscite dart6ul - imx8mp : increase malloc area - fixes for bx50v3 - imx8m: HS400ES and UHS for EVK - imx8qm-rom7720: fix phy bind -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCX+nFGQ8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76byvwCcDhQjWcDIHvNkxD4PVjieTVH4VSsAnifKj0td C8L36yASIlBRxHH4gpGE =39D3 -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2021.1 ---------------- CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680 - fixes for Variscite dart6ul - imx8mp : increase malloc area - fixes for bx50v3 - imx8m: HS400ES and UHS for EVK - imx8qm-rom7720: fix phy bind
This commit is contained in:
Tom Rini
commit
ab865a8ee5
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|
@ -118,8 +118,11 @@
|
|||
|
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&usdhc1 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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||||
};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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|
|
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|
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@ -118,8 +118,11 @@
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|||
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&usdhc1 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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|
|
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|
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@ -174,6 +174,17 @@
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@4 {
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reg = <4>;
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qca,clk-out-frequency = <125000000>;
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};
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};
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};
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&hdmi {
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|
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|
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@ -14,6 +14,10 @@
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chosen {
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stdout-path = &uart1;
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};
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aliases {
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eeprom0 = &eeprom_som;
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};
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};
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&fec1 {
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@ -52,6 +56,10 @@
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};
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};
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&gpio1 {
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u-boot,dm-pre-reloc;
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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@ -96,10 +104,13 @@
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scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
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status = "okay";
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u-boot,dm-pre-reloc;
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eeprom@50 {
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compatible = "cat,24c32";
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eeprom_som: eeprom@50 {
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u-boot,dm-pre-reloc;
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compatible = "atmel,24c04";
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reg = <0x50>;
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status = "okay";
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};
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};
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@ -205,6 +216,7 @@
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};
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pinctrl_i2c2: i2cgrp {
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u-boot,dm-pre-reloc;
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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@ -212,6 +224,7 @@
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};
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pinctrl_i2c2_gpio: i2c2grp_gpio {
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u-boot,dm-pre-reloc;
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
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MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
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@ -10,19 +10,19 @@
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led0 {
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label = "gen_led0";
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gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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led1 {
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label = "gen_led1";
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gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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|
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led2 {
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label = "gen_led2";
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gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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|
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led3 {
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|
|
@ -70,7 +70,7 @@
|
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&ecspi2 {
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&pinctrl_espi2>;
|
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cs-gpios = <&gpio5 9 0>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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eeprom@0 {
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|
|
@ -210,7 +210,7 @@
|
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>;
|
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};
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|
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pinctrl_pcal6414: pcal6414-gpio {
|
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pinctrl_pcal6414: pcal6414-gpiogrp {
|
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fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
|
||||
>;
|
||||
|
|
@ -240,7 +240,7 @@
|
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>;
|
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};
|
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|
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
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fsl,pins = <
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||||
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
|
||||
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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|
|
@ -259,7 +259,7 @@
|
|||
>;
|
||||
};
|
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|
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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@ -271,7 +271,7 @@
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>;
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||||
};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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@ -37,6 +37,10 @@
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/delete-property/ assigned-clock-rates;
|
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
|
||||
};
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|
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&fec1 {
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phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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};
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@ -24,6 +24,26 @@
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cpu-supply = <&buck2_reg>;
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};
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|
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
|
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opp-hz = /bits/ 64 <25000000>;
|
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750M {
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opp-hz = /bits/ 64 <750000000>;
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};
|
||||
};
|
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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@ -52,9 +72,10 @@
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pmic@4b {
|
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
|
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interrupt-parent = <&gpio1>;
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interrupts = <3 GPIO_ACTIVE_LOW>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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@ -116,7 +137,7 @@
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <3000000>;
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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@ -124,7 +145,7 @@
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <900000>;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
|
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regulator-always-on;
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@ -164,7 +185,7 @@
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status = "okay";
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eeprom@50 {
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compatible = "microchip, at24c64d", "atmel,24c64";
|
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compatible = "microchip,24c64", "atmel,24c64";
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
|
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reg = <0x50>;
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@ -190,6 +211,7 @@
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host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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clocks = <&osc_32k>;
|
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max-speed = <4000000>;
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clock-names = "extclk";
|
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};
|
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};
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|
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@ -270,9 +292,9 @@
|
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>;
|
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};
|
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|
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pinctrl_pmic: pmicirq {
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
|
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
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>;
|
||||
};
|
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|
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|
|
@ -289,7 +311,7 @@
|
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>;
|
||||
};
|
||||
|
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pinctrl_usdhc1_gpio: usdhc1grpgpio {
|
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pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
|
||||
>;
|
||||
|
|
@ -306,7 +328,7 @@
|
|||
>;
|
||||
};
|
||||
|
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
|
|
@ -317,7 +339,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
|
|
@ -344,7 +366,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
|
|
@ -360,7 +382,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
|
|
|
|||
|
|
@ -46,6 +46,10 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&pinctrl_reg_usdhc2_vmmc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -96,10 +100,14 @@
|
|||
|
||||
&usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
|
|||
|
|
@ -18,10 +18,18 @@
|
|||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
|
|
@ -29,14 +37,6 @@
|
|||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -68,6 +68,7 @@
|
|||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
|
|
@ -80,6 +81,7 @@
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
|
|
@ -92,6 +94,7 @@
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
|
|
@ -104,6 +107,7 @@
|
|||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
cpu-idle-states = <&cpu_pd_wait>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
|
|
@ -125,7 +129,7 @@
|
|||
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-microvolt = <900000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0xc>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
|
|
@ -204,6 +208,38 @@
|
|||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
|
||||
|
|
@ -227,12 +263,14 @@
|
|||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
|
||||
sai1: sai@30010000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30010000 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -246,6 +284,7 @@
|
|||
};
|
||||
|
||||
sai2: sai@30020000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30020000 0x10000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -273,6 +312,7 @@
|
|||
};
|
||||
|
||||
sai5: sai@30050000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30050000 0x10000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -286,6 +326,7 @@
|
|||
};
|
||||
|
||||
sai6: sai@30060000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
|
||||
reg = <0x30060000 0x10000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -363,6 +404,13 @@
|
|||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mm-tmu";
|
||||
reg = <0x30260000 0x10000>;
|
||||
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
|
|
@ -419,7 +467,7 @@
|
|||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mm-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
|
||||
|
|
@ -455,6 +503,8 @@
|
|||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
|
||||
clock-names = "snvs-pwrkey";
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
|
@ -469,16 +519,20 @@
|
|||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_NOC>,
|
||||
assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
|
||||
<&clk IMX8MM_CLK_A53_CORE>,
|
||||
<&clk IMX8MM_CLK_NOC>,
|
||||
<&clk IMX8MM_CLK_AUDIO_AHB>,
|
||||
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
|
||||
<&clk IMX8MM_SYS_PLL3>,
|
||||
<&clk IMX8MM_VIDEO_PLL1>,
|
||||
<&clk IMX8MM_AUDIO_PLL1>,
|
||||
<&clk IMX8MM_AUDIO_PLL2>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
|
||||
<&clk IMX8MM_ARM_PLL_OUT>,
|
||||
<&clk IMX8MM_SYS_PLL3_OUT>,
|
||||
<&clk IMX8MM_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <0>,
|
||||
assigned-clock-rates = <0>, <0>, <0>,
|
||||
<400000000>,
|
||||
<400000000>,
|
||||
<750000000>,
|
||||
|
|
@ -496,7 +550,8 @@
|
|||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
|
|
@ -555,10 +610,12 @@
|
|||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
<0x8000000 0x8000000 0x10000000>;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
|
|
@ -718,6 +775,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
|
|
@ -760,6 +825,19 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
flexspi: spi@30bb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nxp,imx8mm-fspi";
|
||||
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
|
||||
reg-names = "fspi_base", "fspi_mmap";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MM_CLK_QSPI_ROOT>;
|
||||
clock-names = "fspi", "fspi_en";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
|
|
@ -776,7 +854,8 @@
|
|||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MM_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MM_CLK_ENET_TIMER>,
|
||||
|
|
@ -800,7 +879,8 @@
|
|||
};
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
|
@ -896,7 +976,6 @@
|
|||
ddr-pmu@3d800000 {
|
||||
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
||||
reg = <0x3d800000 0x400000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,6 +47,10 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&pinctrl_uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -93,10 +97,14 @@
|
|||
|
||||
&usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
|
|
|
|||
|
|
@ -48,6 +48,10 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -122,10 +126,14 @@
|
|||
|
||||
&usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
mmc-hs400-1_8v;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
|
@ -293,7 +293,7 @@
|
|||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,ar8031-phy-fixup;
|
||||
fsl,magic-packet;
|
||||
|
|
@ -318,7 +318,7 @@
|
|||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec2>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,ar8031-phy-fixup;
|
||||
fsl,magic-packet;
|
||||
|
|
|
|||
|
|
@ -303,10 +303,11 @@ static int confirm_close(void)
|
|||
static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
int confirmed = argc >= 2 && !strcmp(argv[1], "-y");
|
||||
int err;
|
||||
u16 lc;
|
||||
|
||||
if (!confirm_close())
|
||||
if (!confirmed && !confirm_close())
|
||||
return -EACCES;
|
||||
|
||||
err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
|
||||
|
|
|
|||
|
|
@ -916,7 +916,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
|
|||
}
|
||||
|
||||
if (5 == i) {
|
||||
printf("Fail to set rate to %dkhz", freq);
|
||||
printf("Fail to set rate to %u kHz", freq);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -936,7 +936,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
|
|||
}
|
||||
|
||||
if (best == 0) {
|
||||
printf("Fail to set rate to %dkhz", freq);
|
||||
printf("Fail to set rate to %u kHz", freq);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1115,17 +1115,17 @@ int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||
|
||||
printf("\n");
|
||||
|
||||
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
|
||||
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
|
||||
printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
|
||||
printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
|
||||
printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
|
||||
#endif
|
||||
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
|
||||
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
|
||||
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
|
||||
printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
|
||||
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
|
||||
printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
|
||||
printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
|
||||
printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
|
||||
printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
|
||||
printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
|
||||
printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
|
||||
printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -575,12 +575,6 @@ int board_late_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6-SabreSD\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <spl.h>
|
||||
|
|
|
|||
|
|
@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define VPD_PRODUCT_B650 2
|
||||
#define VPD_PRODUCT_B450 3
|
||||
|
||||
#define AR8033_DBG_REG_ADDR 0x1d
|
||||
#define AR8033_DBG_REG_DATA 0x1e
|
||||
#define AR8033_SERDES_REG 0x5
|
||||
|
||||
static int productid; /* Default to generic. */
|
||||
static struct vpd_cache vpd;
|
||||
|
||||
|
|
@ -61,31 +65,16 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mx6_rgmii_rework(struct phy_device *phydev)
|
||||
{
|
||||
/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
|
||||
/* set device address 0x7 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
/* offset 0x8016: CLK_25M Clock Select */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
||||
/* enable register write, no post increment, address 0x7 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
||||
/* set to 125 MHz from local PLL source */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
/* set debug port address: SerDes Test and System Mode Control */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
/* enable rgmii tx clock delay */
|
||||
/* set the reserved bits to avoid board specific voltage peak issue*/
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
mx6_rgmii_rework(phydev);
|
||||
/*
|
||||
* Set reserved bits to avoid board specific voltage peak issue. The
|
||||
* value is a magic number provided directly by Qualcomm. Note, that
|
||||
* PHY driver will take control of BIT(8) in this register to control
|
||||
* TX clock delay, so we do not initialize that bit here.
|
||||
*/
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
|
@ -356,15 +345,12 @@ static void process_vpd(struct vpd_cache *vpd)
|
|||
|
||||
switch (vpd->product_id) {
|
||||
case VPD_PRODUCT_B450:
|
||||
env_set("confidx", "1");
|
||||
i210_index = 1;
|
||||
break;
|
||||
case VPD_PRODUCT_B650:
|
||||
env_set("confidx", "2");
|
||||
i210_index = 1;
|
||||
break;
|
||||
case VPD_PRODUCT_B850:
|
||||
env_set("confidx", "3");
|
||||
i210_index = 2;
|
||||
break;
|
||||
}
|
||||
|
|
@ -554,16 +540,23 @@ int ft_board_setup(void *blob, struct bd_info *bd)
|
|||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
const char *machine = name;
|
||||
|
||||
if (!vpd.is_read)
|
||||
return strcmp(name, "imx6q-bx50v3");
|
||||
|
||||
if (!strncmp(machine, "Boot ", 5))
|
||||
machine += 5;
|
||||
if (!strncmp(machine, "imx6q-", 6))
|
||||
machine += 6;
|
||||
|
||||
switch (vpd.product_id) {
|
||||
case VPD_PRODUCT_B450:
|
||||
return strcmp(name, "imx6q-b450v3");
|
||||
return strcasecmp(machine, "b450v3");
|
||||
case VPD_PRODUCT_B650:
|
||||
return strcmp(name, "imx6q-b650v3");
|
||||
return strcasecmp(machine, "b650v3");
|
||||
case VPD_PRODUCT_B850:
|
||||
return strcmp(name, "imx6q-b850v3");
|
||||
return strcasecmp(machine, "b850v3");
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Apalis iMX8X
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
S: Maintained
|
||||
F: arch/arm/dts/fsl-imx8x-apalis.dts
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Apalis iMX6
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Colibri iMX6ULL
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Colibri iMX6
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Colibri iMX7
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
COLIBRI_T20
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_t20/
|
||||
F: include/configs/colibri_t20.h
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Colibri T30
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_t30/
|
||||
F: include/configs/colibri_t30.h
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Colibri VFxx
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Verdin iMX8M Mini
|
||||
M: Igor Opaniuk <igor.opaniuk@toradex.com>
|
||||
M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
|
||||
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
|
||||
S: Maintained
|
||||
F: arch/arm/dts/imx8mm-verdin.dts
|
||||
|
|
|
|||
|
|
@ -12,8 +12,11 @@
|
|||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <dm.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <i2c_eeprom.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <malloc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <usb.h>
|
||||
|
|
@ -222,9 +225,108 @@ int board_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* length of strings stored in the eeprom */
|
||||
#define DART6UL_PN_LEN 16
|
||||
#define DART6UL_ASSY_LEN 16
|
||||
#define DART6UL_DATE_LEN 12
|
||||
|
||||
/* eeprom content, 512 bytes */
|
||||
struct dart6ul_info {
|
||||
u32 magic;
|
||||
u8 partnumber[DART6UL_PN_LEN];
|
||||
u8 assy[DART6UL_ASSY_LEN];
|
||||
u8 date[DART6UL_DATE_LEN];
|
||||
u32 custom_addr_val[32];
|
||||
struct cmd {
|
||||
u8 addr;
|
||||
u8 index;
|
||||
} custom_cmd[150];
|
||||
u8 res[33];
|
||||
u8 som_info;
|
||||
u8 ddr_size;
|
||||
u8 crc;
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
|
||||
#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1)
|
||||
#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3)
|
||||
#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8)
|
||||
#define DART6UL_INFO_MAGIC 0x32524156
|
||||
|
||||
static const char *som_info_storage_to_str(u8 som_info)
|
||||
{
|
||||
switch (DART6UL_INFO_STORAGE_GET(som_info)) {
|
||||
case 0x0: return "none (SD only)";
|
||||
case 0x1: return "NAND";
|
||||
case 0x2: return "eMMC";
|
||||
default: return "unknown";
|
||||
}
|
||||
}
|
||||
|
||||
static const char *som_info_rev_to_str(u8 som_info)
|
||||
{
|
||||
switch (DART6UL_INFO_REV_GET(som_info)) {
|
||||
case 0x0: return "2.4G";
|
||||
case 0x1: return "5G";
|
||||
default: return "unknown";
|
||||
}
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Variscite DART-6UL Evaluation Kit\n");
|
||||
const char *path = "eeprom0";
|
||||
struct dart6ul_info *info;
|
||||
struct udevice *dev;
|
||||
int ret, off;
|
||||
|
||||
off = fdt_path_offset(gd->fdt_blob, path);
|
||||
if (off < 0) {
|
||||
printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
|
||||
return off;
|
||||
}
|
||||
|
||||
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
|
||||
if (ret) {
|
||||
printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
info = malloc(sizeof(struct dart6ul_info));
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
|
||||
sizeof(struct dart6ul_info));
|
||||
if (ret) {
|
||||
printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
|
||||
free(info);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (info->magic != DART6UL_INFO_MAGIC) {
|
||||
printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
|
||||
info->magic, DART6UL_INFO_MAGIC);
|
||||
/* do not fail if the content is invalid */
|
||||
free(info);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* make sure strings are null terminated */
|
||||
info->partnumber[DART6UL_PN_LEN - 1] = '\0';
|
||||
info->assy[DART6UL_ASSY_LEN - 1] = '\0';
|
||||
info->date[DART6UL_DATE_LEN - 1] = '\0';
|
||||
|
||||
printf("Board: PN: %s, Assy: %s, Date: %s\n"
|
||||
" Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
|
||||
info->partnumber,
|
||||
info->assy,
|
||||
info->date,
|
||||
som_info_storage_to_str(info->som_info),
|
||||
DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
|
||||
DART6UL_DDRSIZE_IN_MIB(info->ddr_size),
|
||||
som_info_rev_to_str(info->som_info));
|
||||
|
||||
free(info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,6 +70,13 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_SPL_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
|
|
|
|||
|
|
@ -66,6 +66,10 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
|
|
|
|||
|
|
@ -65,6 +65,10 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40200000
|
|||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
|
|
@ -70,6 +70,9 @@ CONFIG_LED_GPIO=y
|
|||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_I2C_GPIO=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
|||
|
|
@ -954,7 +954,7 @@ static int mxc_i2c_probe(struct udevice *bus)
|
|||
!dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
|
||||
ret || ret2) {
|
||||
dev_err(bus,
|
||||
"i2c bus %d at %lu, fail to request scl/sda gpio\n",
|
||||
"i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
|
||||
bus->seq, i2c_bus->base);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#define __COMPILER_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef USE_HOSTCC
|
||||
|
||||
|
|
@ -150,4 +151,12 @@ typedef unsigned long int uintptr_t;
|
|||
#define MEM_SUPPORT_64BIT_DATA 0
|
||||
#endif
|
||||
|
||||
static inline bool host_build(void) {
|
||||
#ifdef USE_HOSTCC
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
"networkboot=" \
|
||||
"run setnetworkboot; " \
|
||||
"nfs ${loadaddr} /srv/nfs/fitImage; " \
|
||||
"bootm ${loadaddr}#conf@${confidx}\0" \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_NETWORKBOOTCOMMAND \
|
||||
"run networkboot; " \
|
||||
|
|
@ -111,7 +111,7 @@
|
|||
"doboot=" \
|
||||
"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
|
||||
"run setargs; " \
|
||||
"bootm ${loadaddr}#conf@${confidx}\0" \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"tryboot=" \
|
||||
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
|
||||
"run loadimage || run swappartitions && run loadimage || " \
|
||||
|
|
|
|||
|
|
@ -248,6 +248,32 @@
|
|||
#define IMX8MM_CLK_SNVS_ROOT 228
|
||||
#define IMX8MM_CLK_GIC 229
|
||||
|
||||
#define IMX8MM_CLK_END 230
|
||||
#define IMX8MM_SYS_PLL1_40M_CG 230
|
||||
#define IMX8MM_SYS_PLL1_80M_CG 231
|
||||
#define IMX8MM_SYS_PLL1_100M_CG 232
|
||||
#define IMX8MM_SYS_PLL1_133M_CG 233
|
||||
#define IMX8MM_SYS_PLL1_160M_CG 234
|
||||
#define IMX8MM_SYS_PLL1_200M_CG 235
|
||||
#define IMX8MM_SYS_PLL1_266M_CG 236
|
||||
#define IMX8MM_SYS_PLL1_400M_CG 237
|
||||
#define IMX8MM_SYS_PLL2_50M_CG 238
|
||||
#define IMX8MM_SYS_PLL2_100M_CG 239
|
||||
#define IMX8MM_SYS_PLL2_125M_CG 240
|
||||
#define IMX8MM_SYS_PLL2_166M_CG 241
|
||||
#define IMX8MM_SYS_PLL2_200M_CG 242
|
||||
#define IMX8MM_SYS_PLL2_250M_CG 243
|
||||
#define IMX8MM_SYS_PLL2_333M_CG 244
|
||||
#define IMX8MM_SYS_PLL2_500M_CG 245
|
||||
|
||||
#define IMX8MM_CLK_M4_CORE 246
|
||||
#define IMX8MM_CLK_VPU_CORE 247
|
||||
#define IMX8MM_CLK_GPU3D_CORE 248
|
||||
#define IMX8MM_CLK_GPU2D_CORE 249
|
||||
|
||||
#define IMX8MM_CLK_CLKO2 250
|
||||
|
||||
#define IMX8MM_CLK_A53_CORE 251
|
||||
|
||||
#define IMX8MM_CLK_END 252
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue