mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
50b1a69cee
i.MX8M series provide support for high speed grades in their usdhc controllers, which has eMMC and SDHC connected to them. Enable this support across the entire i.MX8M family by providing quirks to usdhc controllers designated by storage media connected to them. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com>
129 lines
1.1 KiB
Plaintext
129 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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&{/imx8qx-pm} {
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u-boot,dm-spl;
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};
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&mu {
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u-boot,dm-spl;
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};
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&clk {
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u-boot,dm-spl;
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};
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&iomuxc {
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u-boot,dm-spl;
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};
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&pd_lsio {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio0 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio1 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio2 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio3 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio4 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio5 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio6 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio7 {
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u-boot,dm-spl;
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};
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&pd_conn {
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u-boot,dm-spl;
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};
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&pd_conn_sdch0 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch1 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch2 {
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u-boot,dm-spl;
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};
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&pd_dma {
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u-boot,dm-spl;
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};
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&pd_dma_lpuart0 {
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u-boot,dm-spl;
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&gpio6 {
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u-boot,dm-spl;
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};
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&gpio7 {
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u-boot,dm-spl;
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};
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&lpuart0 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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