From 2055103f0848cfbb773420057e2e38c76aceb697 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Dec 2020 15:26:16 +0100 Subject: [PATCH 01/19] ARM: dts: imx: imx8qm-rom7720: Fix AR8031 phy-mode Fixed wrong PHY Interface Mode As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Fix the phy-mode accordingly to fix the regression. Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Vladimir Oltean --- arch/arm/dts/imx8qm-rom7720-a1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index 5f9ac955ed..d1f2fff869 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -293,7 +293,7 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,ar8031-phy-fixup; fsl,magic-packet; @@ -318,7 +318,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,ar8031-phy-fixup; fsl,magic-packet; From d72cecec7fc0b04d6d52df44ae1e7033ee7e4099 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 4 Dec 2020 17:27:45 -0600 Subject: [PATCH 02/19] imx: imx8mm: Update clock bindings header Import clock bindings header file from Linux 5.10-rc6 Signed-off-by: Adam Ford Acked-by: Peng Fan --- include/dt-bindings/clock/imx8mm-clock.h | 28 +++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c686f3..e63a5530ae 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,32 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif From 15d79fcac09fee7d27ff0a0c36389433507ce3bd Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 4 Dec 2020 17:27:46 -0600 Subject: [PATCH 03/19] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 There have been some updates to the device tree since 5.6. This also includes some clocks, and makes it easier to keep board device tree files in sync with Linux Signed-off-by: Adam Ford Acked-by: Peng Fan --- arch/arm/dts/imx8mm.dtsi | 119 ++++++++++++++++++++++++++++++++------- 1 file changed, 99 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 1e5e11592f..05ee062548 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -18,10 +18,18 @@ aliases { ethernet0 = &fec1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -29,14 +37,6 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; }; cpus { @@ -68,6 +68,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -80,6 +81,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -92,6 +94,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -104,6 +107,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -125,7 +129,7 @@ opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; + opp-microvolt = <950000>; opp-supported-hw = <0xc>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -204,6 +208,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -227,12 +263,14 @@ ranges = <0x0 0x0 0x0 0x3e000000>; aips1: bus@30000000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = ; @@ -246,6 +284,7 @@ }; sai2: sai@30020000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = ; @@ -273,6 +312,7 @@ }; sai5: sai@30050000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = ; @@ -286,6 +326,7 @@ }; sai6: sai@30060000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = ; @@ -363,6 +404,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -419,7 +467,7 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; @@ -455,6 +503,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs-pwrkey"; linux,keycode = ; wakeup-source; status = "disabled"; @@ -469,16 +519,20 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, + assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_CLK_A53_CORE>, + <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <750000000>, @@ -496,7 +550,8 @@ }; aips2: bus@30400000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30400000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; @@ -555,10 +610,12 @@ }; aips3: bus@30800000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30800000 0x400000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -718,6 +775,14 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -760,6 +825,19 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -776,7 +854,8 @@ reg = <0x30be0000 0x10000>; interrupts = , , - ; + , + ; clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET_TIMER>, @@ -800,7 +879,8 @@ }; aips4: bus@32c00000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -896,7 +976,6 @@ ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; interrupts = ; }; }; From 1170d2b759096af0e7ba6ffaf6abde286a7d6595 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 4 Dec 2020 17:27:47 -0600 Subject: [PATCH 04/19] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 There have been some updates to the device trees, so re-sync. Signed-off-by: Adam Ford Acked-by: Peng Fan --- arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 16 ++++----- arch/arm/dts/imx8mm-beacon-som.dtsi | 44 +++++++++++++++++------ 2 files changed, 41 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index baa5f997d0..d6b9dedd16 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -10,19 +10,19 @@ led0 { label = "gen_led0"; gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led1 { label = "gen_led1"; gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led2 { label = "gen_led2"; gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led3 { @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 { @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index 801bd02eae..b88c3c99b0 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -24,6 +24,26 @@ cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -52,9 +72,10 @@ pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -116,7 +137,7 @@ ldo1_reg: LDO1 { regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -124,7 +145,7 @@ ldo2_reg: LDO2 { regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; @@ -164,7 +185,7 @@ status = "okay"; eeprom@50 { - compatible = "microchip, at24c64d", "atmel,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -190,6 +211,7 @@ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; + max-speed = <4000000>; clock-names = "extclk"; }; }; @@ -270,9 +292,9 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; @@ -289,7 +311,7 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1grpgpio { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; @@ -306,7 +328,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 @@ -317,7 +339,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 @@ -344,7 +366,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -360,7 +382,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 From 1a5d9c84b47239ea527f5d8eaa19f35b7fdacb8f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 4 Dec 2020 18:59:43 -0600 Subject: [PATCH 05/19] imx8mm_beacon: Enable HS400 on MMC controller The i.MX8MM is capable of HS400. Enable it in both U-Boot and SPL for faster throughput. Signed-off-by: Adam Ford --- configs/imx8mm_beacon_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index c5d331f617..49d5453078 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -70,6 +70,13 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y From 247bbeb74c186963d9365db3136d0285618bd9a7 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Sat, 5 Dec 2020 17:29:17 +0000 Subject: [PATCH 06/19] ARM: dts: imx8m: increase off-on delay on the SD Vcc regulator Some SD Card controller and power circuitry has increased capacitance, which keeps the internal logic remains powered after regulator is switch off. This is generally the case when card is switched to SD104 mode, where a power cycle should be performed. In case if the card internal logic remains powered, it causes a subsequent failure of mode transition, effectively leading to failed enumeration. Introduce a delay of 20 msec in order to provide a possibility for internal card circuitry to drain voltages and perform a power cycle correctly. Similar fix is done in commit c49d0ac38a76 ("ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator") targeted Renesas SOCs. Signed-off-by: Andrey Zhizhikin Cc: Stefano Babic --- arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 5 +++++ arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 5 +++++ 6 files changed, 26 insertions(+) create mode 100644 arch/arm/dts/imx8mq-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-phanbell-u-boot.dtsi diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index fc1aebb2fe..6d80a529ae 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -37,6 +37,10 @@ /delete-property/ assigned-clock-rates; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index b5c12105a9..9f77d3c6ff 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -46,6 +46,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_reg_usdhc2_vmmc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 4419679d4c..98b0b9891b 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -47,6 +47,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_uart2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 24a93ac2d6..2452e9175c 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -48,6 +48,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + ®_usdhc2_vmmc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi new file mode 100644 index 0000000000..4712cf6a44 --- /dev/null +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi new file mode 100644 index 0000000000..4712cf6a44 --- /dev/null +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; From 50b1a69cee0dc06d0c713a5a978998f2b4a9cb31 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Sat, 5 Dec 2020 17:29:18 +0000 Subject: [PATCH 07/19] ARM: dts: imx8m: add UHS or HS400/HS400ES properties i.MX8M series provide support for high speed grades in their usdhc controllers, which has eMMC and SDHC connected to them. Enable this support across the entire i.MX8M family by providing quirks to usdhc controllers designated by storage media connected to them. Signed-off-by: Andrey Zhizhikin Cc: Stefano Babic Cc: Ye Li --- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 3 +++ arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 3 +++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 9 +++++++++ 6 files changed, 27 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 80d6475b7c..9e0d264b71 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 771ab635f1..701af4434d 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 9f77d3c6ff..e843a5648e 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -100,10 +100,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &i2c1 { diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 98b0b9891b..025090fff4 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -97,10 +97,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 2452e9175c..4f00b5a3a9 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -126,10 +126,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 4712cf6a44..44af663727 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -3,3 +3,12 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; + +&usdhc1 { + mmc-hs400-1_8v; +}; + +&usdhc2 { + sd-uhs-sdr104; + sd-uhs-ddr50; +}; From e601f0f9c966e5485a4b7d950082b97c81af3151 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Sat, 5 Dec 2020 17:29:19 +0000 Subject: [PATCH 08/19] configs: imx8m: enable eMMC HS400ES and SD UHS mode on EVK i.MX8M series includes support for high speed modes in uSDHC controllers. Turn on corresponding configuration options for EVK boards, which would enable high speed modes to be included in U-Boot. Signed-off-by: Andrey Zhizhikin --- configs/imx8mm_evk_defconfig | 4 ++++ configs/imx8mn_ddr4_evk_defconfig | 4 ++++ configs/imx8mp_evk_defconfig | 3 +++ 3 files changed, 11 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 91d3bc3ac9..1aef1ab40d 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -66,6 +66,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 22e5f5aeea..41889c4624 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -65,6 +65,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index cd5724e811..f84696f030 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -70,6 +70,9 @@ CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y From 72397c9621ab37f117ac171d3090f11a2e6b33d6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 14 Dec 2020 14:32:39 -0300 Subject: [PATCH 09/19] mx6sabresd: Remove unneeded checkboard() After the conversion to device tree the board information becomes redundant: Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board Board: MX6-SabreSD Remove the printing of the board information. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- board/freescale/mx6sabresd/mx6sabresd.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 0d343da519..9a176f4711 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -575,12 +575,6 @@ int board_late_init(void) return 0; } -int checkboard(void) -{ - puts("Board: MX6-SabreSD\n"); - return 0; -} - #ifdef CONFIG_SPL_BUILD #include #include From db43c0b72d1eb0dcf2778413743fcf355b5632a1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 15 Dec 2020 00:41:53 +0100 Subject: [PATCH 10/19] compiler.h: add host_build() Add a host_build() function, so that it's possible to check for software being build with USE_HOSTCC without relying on preprocessor conditions. In other words #ifdef USE_HOSTCC host_only_code(); #endif can be written like this instead: if (host_build()) host_only_code(); This improves code readability and test coverage and compiler will eleminate this unreachable code. Signed-off-by: Sebastian Reichel Reviewed-by: Simon Glass --- include/compiler.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/compiler.h b/include/compiler.h index 90b7afae53..27b9843497 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -6,6 +6,7 @@ #define __COMPILER_H__ #include +#include #ifdef USE_HOSTCC @@ -150,4 +151,12 @@ typedef unsigned long int uintptr_t; #define MEM_SUPPORT_64BIT_DATA 0 #endif +static inline bool host_build(void) { +#ifdef USE_HOSTCC + return true; +#else + return false; +#endif +} + #endif From c44d374bef118a07b44a5a5f596569891cfc6d21 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 15 Dec 2020 00:41:56 +0100 Subject: [PATCH 11/19] board: ge: bx50v3: remove confidx magic numbers Instead of hardcoding index magic numbers in the board code, also rely on board_fit_config_name_match choosing the right config for the fitImage containing the kernel. Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 16 ++++++++++------ include/configs/ge_bx50v3.h | 4 ++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 4754647fb4..a3ae037a82 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -356,15 +356,12 @@ static void process_vpd(struct vpd_cache *vpd) switch (vpd->product_id) { case VPD_PRODUCT_B450: - env_set("confidx", "1"); i210_index = 1; break; case VPD_PRODUCT_B650: - env_set("confidx", "2"); i210_index = 1; break; case VPD_PRODUCT_B850: - env_set("confidx", "3"); i210_index = 2; break; } @@ -554,16 +551,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) int board_fit_config_name_match(const char *name) { + const char *machine = name; + if (!vpd.is_read) return strcmp(name, "imx6q-bx50v3"); + if (!strncmp(machine, "Boot ", 5)) + machine += 5; + if (!strncmp(machine, "imx6q-", 6)) + machine += 6; + switch (vpd.product_id) { case VPD_PRODUCT_B450: - return strcmp(name, "imx6q-b450v3"); + return strcasecmp(machine, "b450v3"); case VPD_PRODUCT_B650: - return strcmp(name, "imx6q-b650v3"); + return strcasecmp(machine, "b650v3"); case VPD_PRODUCT_B850: - return strcmp(name, "imx6q-b850v3"); + return strcasecmp(machine, "b850v3"); default: return -1; } diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index e5c580b3f9..2d854af9a0 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -62,7 +62,7 @@ "networkboot=" \ "run setnetworkboot; " \ "nfs ${loadaddr} /srv/nfs/fitImage; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ #define CONFIG_NETWORKBOOTCOMMAND \ "run networkboot; " \ @@ -111,7 +111,7 @@ "doboot=" \ "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ "run setargs; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ "tryboot=" \ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run loadimage || run swappartitions && run loadimage || " \ From 717bf50f4b362c1f4fac5ac9f030fab5bed9cf65 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 15 Dec 2020 00:41:57 +0100 Subject: [PATCH 12/19] board: ge: bx50v3: cleanup phy config The current PHY rework does the following things: 1. Configure 125MHz clock 2. Setup the TX clock delay (RX is enabled by default), 3. Setup reserved bits to avoid voltage peak The clock delays are nowadays already configured by the PHY driver (in ar803x_delay_config). The code for that can simply be dropped. The clock speed can also be configured by the PHY driver by adding the device tree property "qca,clk-out-frequency". What is left is setting up the undocumented reserved bits to avoid the voltage peak problem. I slightly improved its documentation while updating the board's PHY rework code. Signed-off-by: Sebastian Reichel --- arch/arm/dts/imx6q-ba16.dtsi | 11 +++++++++++ board/ge/bx50v3/bx50v3.c | 35 ++++++++++++----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi index 7d8f61f2fd..9da2bb6e86 100644 --- a/arch/arm/dts/imx6q-ba16.dtsi +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -174,6 +174,17 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; status = "okay"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi { diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index a3ae037a82..3ea9425fd1 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR; #define VPD_PRODUCT_B650 2 #define VPD_PRODUCT_B450 3 +#define AR8033_DBG_REG_ADDR 0x1d +#define AR8033_DBG_REG_DATA 0x1e +#define AR8033_SERDES_REG 0x5 + static int productid; /* Default to generic. */ static struct vpd_cache vpd; @@ -61,31 +65,16 @@ int dram_init(void) return 0; } -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ - /* set device address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - /* offset 0x8016: CLK_25M Clock Select */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - /* enable register write, no post increment, address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - /* set to 125 MHz from local PLL source */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); - - /* rgmii tx clock delay enable */ - /* set debug port address: SerDes Test and System Mode Control */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - /* enable rgmii tx clock delay */ - /* set the reserved bits to avoid board specific voltage peak issue*/ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); - - return 0; -} - int board_phy_config(struct phy_device *phydev) { - mx6_rgmii_rework(phydev); + /* + * Set reserved bits to avoid board specific voltage peak issue. The + * value is a magic number provided directly by Qualcomm. Note, that + * PHY driver will take control of BIT(8) in this register to control + * TX clock delay, so we do not initialize that bit here. + */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47); if (phydev->drv->config) phydev->drv->config(phydev); From 7d6a36a48d8226d363f8a4fab618e04b2a65e2cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Mon, 21 Dec 2020 18:31:28 +0100 Subject: [PATCH 13/19] imx: ahab: allow to bypass confirmation for ahab_close cmd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling ahab_close cmd force the user to interact for confirmation. This is not user-friendly when using this cmd during factory process. Allow the user to pass '-y' option to bypass this confirmation. Signed-off-by: Clément Péron Reviewed-by: Peng Fan Acked-by: Oliver Graute --- arch/arm/mach-imx/imx8/ahab.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 4bb7c46921..600a1108ce 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -303,10 +303,11 @@ static int confirm_close(void) static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; u16 lc; - if (!confirm_close()) + if (!confirmed && !confirm_close()) return -EACCES; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); From b6b1b38a94b45c4580b52076c0aa5f72cc3ce0eb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 21 Dec 2020 15:40:37 -0300 Subject: [PATCH 14/19] imx8mp_evk: Increase CONFIG_SYS_MALLOC_F_LEN When booting imx8mp-evk the following allocation error message is seen: U-Boot 2021.01-rc3-00200-ge668bec96a5f (Dec 21 2020 - 14:36:42 -0300) alloc space exhausted Fix it by increasing CONFIG_SYS_MALLOC_F_LEN to 0x10000 like it is done on other i.MX8MM/8MN boards. Reported-by: Andrey Zhizhikin Signed-off-by: Fabio Estevam Tested-by: Andrey Zhizhikin Reviewed-by: Peng Fan --- configs/imx8mp_evk_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index f84696f030..6166d103e3 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y From f23c7068633d6087a4909b2cd0d83a62689a7d47 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 22 Dec 2020 17:56:46 +0200 Subject: [PATCH 15/19] toradex: hand over maintainership Hand over maintainership of Toradex SoMs (that I was responsible of) to Oleksandr because of my resignation from Toradex, as such I will have no immediate involvement with these modules and as a result not able to continue maintaining these boards. CC: Oleksandr Suvorov Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov Acked-by: Oleksandr Suvorov --- board/toradex/apalis-imx8x/MAINTAINERS | 2 +- board/toradex/apalis_imx6/MAINTAINERS | 2 +- board/toradex/colibri-imx6ull/MAINTAINERS | 2 +- board/toradex/colibri_imx6/MAINTAINERS | 2 +- board/toradex/colibri_imx7/MAINTAINERS | 2 +- board/toradex/colibri_t20/MAINTAINERS | 2 +- board/toradex/colibri_t30/MAINTAINERS | 2 +- board/toradex/colibri_vf/MAINTAINERS | 2 +- board/toradex/verdin-imx8mm/MAINTAINERS | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS index fbf9379931..5272154447 100644 --- a/board/toradex/apalis-imx8x/MAINTAINERS +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX8X -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software S: Maintained F: arch/arm/dts/fsl-imx8x-apalis.dts diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 4a2707e771..fde4d92dc3 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX6 -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 4107d29876..899b1ff555 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6ULL -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 76f9446bba..2cbf65433d 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6 -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 61a504487a..3d7d010d8a 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX7 -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index 2a8e6fb74b..61fbd2c1e0 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Igor Opaniuk +M: Oleksandr Suvorov S: Maintained F: board/toradex/colibri_t20/ F: include/configs/colibri_t20.h diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS index 00c03c89b8..ded9e28295 100644 --- a/board/toradex/colibri_t30/MAINTAINERS +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -1,5 +1,5 @@ Colibri T30 -M: Igor Opaniuk +M: Oleksandr Suvorov S: Maintained F: board/toradex/colibri_t30/ F: include/configs/colibri_t30.h diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index f94cc0fbe2..c6627654a2 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,5 +1,5 @@ Colibri VFxx -M: Igor Opaniuk +M: Oleksandr Suvorov W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 2495696e9d..08c370178c 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -1,5 +1,5 @@ Verdin iMX8M Mini -M: Igor Opaniuk +M: Oleksandr Suvorov W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin.dts From d4d7b663b8cae5ef4209aaef21a2435a7d5d4dd7 Mon Sep 17 00:00:00 2001 From: Marc Ferland Date: Tue, 22 Dec 2020 14:24:11 -0500 Subject: [PATCH 16/19] arm: dart6ul: change compatible string for eeprom The eeprom at address 0x50 is a BR24G04NUX-3TTR. It has a 4Kbit (512x8) capacity, change the compatible string to reflect this fact. Also, add an alias to easily refer to this eeprom with fdt_path_offset() which will be in another commit. Signed-off-by: Marc Ferland Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ull-dart-6ul.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index e96669f493..fed40b0109 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -14,6 +14,10 @@ chosen { stdout-path = &uart1; }; + + aliases { + eeprom0 = &eeprom_som; + }; }; &fec1 { @@ -97,9 +101,10 @@ sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; - eeprom@50 { - compatible = "cat,24c32"; + eeprom_som: eeprom@50 { + compatible = "atmel,24c04"; reg = <0x50>; + status = "okay"; }; }; From 37648b600cd16848e689e341b20da71356e24212 Mon Sep 17 00:00:00 2001 From: Marc Ferland Date: Tue, 22 Dec 2020 14:24:12 -0500 Subject: [PATCH 17/19] arm: dart6ul: read and print SoM info from eeprom on startup The dart6ul has an i2c eeprom at 0x50 which contains, among other things, the manufacturing/revision/options info of the SoM. This patch replaces the current checkboard() implementation with a more exhaustive one based on the content of the eeprom. Since this code uses the new driver model, some changes were also required in the DTS to make the nodes related to i2c available before relocation. This code was inspired from the supported u-boot code from Variscite which can be found here: https://github.com/varigit/uboot-imx/tree/imx_v2018.03_4.14.78_1.0.0_ga_var02 New output example: Board: PN: VSM-6UL-705B, Assy: AS1812142257, Date: 2019 Feb 17 Storage: eMMC, Wifi: yes, DDR: 1024 MiB, Rev: 2.4G Signed-off-by: Marc Ferland Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ull-dart-6ul.dtsi | 8 +++ board/variscite/dart_6ul/dart_6ul.c | 104 +++++++++++++++++++++++++++- configs/variscite_dart6ul_defconfig | 2 + 3 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index fed40b0109..805a382da9 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -56,6 +56,10 @@ }; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -100,8 +104,10 @@ scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; + u-boot,dm-pre-reloc; eeprom_som: eeprom@50 { + u-boot,dm-pre-reloc; compatible = "atmel,24c04"; reg = <0x50>; status = "okay"; @@ -210,6 +216,7 @@ }; pinctrl_i2c2: i2cgrp { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 @@ -217,6 +224,7 @@ }; pinctrl_i2c2_gpio: i2c2grp_gpio { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c index d8e383d323..360be758bb 100644 --- a/board/variscite/dart_6ul/dart_6ul.c +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -12,8 +12,11 @@ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -222,9 +225,108 @@ int board_init(void) return 0; } +/* length of strings stored in the eeprom */ +#define DART6UL_PN_LEN 16 +#define DART6UL_ASSY_LEN 16 +#define DART6UL_DATE_LEN 12 + +/* eeprom content, 512 bytes */ +struct dart6ul_info { + u32 magic; + u8 partnumber[DART6UL_PN_LEN]; + u8 assy[DART6UL_ASSY_LEN]; + u8 date[DART6UL_DATE_LEN]; + u32 custom_addr_val[32]; + struct cmd { + u8 addr; + u8 index; + } custom_cmd[150]; + u8 res[33]; + u8 som_info; + u8 ddr_size; + u8 crc; +} __attribute__ ((__packed__)); + +#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3) +#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1) +#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3) +#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8) +#define DART6UL_INFO_MAGIC 0x32524156 + +static const char *som_info_storage_to_str(u8 som_info) +{ + switch (DART6UL_INFO_STORAGE_GET(som_info)) { + case 0x0: return "none (SD only)"; + case 0x1: return "NAND"; + case 0x2: return "eMMC"; + default: return "unknown"; + } +} + +static const char *som_info_rev_to_str(u8 som_info) +{ + switch (DART6UL_INFO_REV_GET(som_info)) { + case 0x0: return "2.4G"; + case 0x1: return "5G"; + default: return "unknown"; + } +} + int checkboard(void) { - puts("Board: Variscite DART-6UL Evaluation Kit\n"); + const char *path = "eeprom0"; + struct dart6ul_info *info; + struct udevice *dev; + int ret, off; + + off = fdt_path_offset(gd->fdt_blob, path); + if (off < 0) { + printf("%s: fdt_path_offset() failed: %d\n", __func__, off); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret); + return ret; + } + + info = malloc(sizeof(struct dart6ul_info)); + if (!info) + return -ENOMEM; + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)info, + sizeof(struct dart6ul_info)); + if (ret) { + printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret); + free(info); + return ret; + } + + if (info->magic != DART6UL_INFO_MAGIC) { + printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n", + info->magic, DART6UL_INFO_MAGIC); + /* do not fail if the content is invalid */ + free(info); + return 0; + } + + /* make sure strings are null terminated */ + info->partnumber[DART6UL_PN_LEN - 1] = '\0'; + info->assy[DART6UL_ASSY_LEN - 1] = '\0'; + info->date[DART6UL_DATE_LEN - 1] = '\0'; + + printf("Board: PN: %s, Assy: %s, Date: %s\n" + " Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n", + info->partnumber, + info->assy, + info->date, + som_info_storage_to_str(info->som_info), + DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no", + DART6UL_DDRSIZE_IN_MIB(info->ddr_size), + som_info_rev_to_str(info->som_info)); + + free(info); return 0; } diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 5f94cea5dd..721882567d 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -36,6 +36,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PHYLIB=y From e6abe163bf0b81d2ff6cfbc849252bb30b0d6a19 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 25 Dec 2020 16:22:27 +0100 Subject: [PATCH 18/19] imx: mx7: clock: use correct format strings Use %u and not %d for unsigned values. Print kHz and not khz. Signed-off-by: Heinrich Schuchardt Reviewed-by: Peng Fan --- arch/arm/mach-imx/mx7/clock.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index aba9461d92..6a1bad855e 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -916,7 +916,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (5 == i) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } } @@ -936,7 +936,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (best == 0) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } @@ -1115,17 +1115,17 @@ int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, printf("\n"); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); #endif - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); - printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); - printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); return 0; } From 26c7048dd9d04158a23e9dbfe3f0dccc4febcaed Mon Sep 17 00:00:00 2001 From: Marc Ferland Date: Mon, 21 Dec 2020 09:50:16 -0500 Subject: [PATCH 19/19] i2c: mxc_i2c: improve error message readability Use 0x%2lx to print the i2c bus base address in hexadecimal format instead of printing as an integer. Signed-off-by: Marc Ferland Reviewed-by: Fabio Estevam --- drivers/i2c/mxc_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 7609594bd0..d486dab043 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -954,7 +954,7 @@ static int mxc_i2c_probe(struct udevice *bus) !dm_gpio_is_valid(&i2c_bus->scl_gpio) || ret || ret2) { dev_err(bus, - "i2c bus %d at %lu, fail to request scl/sda gpio\n", + "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); return -EINVAL; }